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PT7V4050MDTHA28.000

Description
PLL/Frequency Synthesis Circuit,
CategoryAnalog mixed-signal IC    The signal circuit   
File Size85KB,7 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Download Datasheet Parametric View All

PT7V4050MDTHA28.000 Overview

PLL/Frequency Synthesis Circuit,

PT7V4050MDTHA28.000 Parametric

Parameter NameAttribute value
Objectid113585169
package instruction,
Reach Compliance Codeunknown
ECCN codeEAR99
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
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Features
• PLL with quartz stabilized VCXO
• Loss of signals alarm
• Return to nominal clock upon LOS
• Input data rates from 8 kb/s to 65 Mb/s
• Tri-state output
• User defined PLL loop response
• NRZ data compatible
3.3V and
5.0V power supply
General Description
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Crystal Frequencies Supported:
12.000~65.536 MHz
Block Diagram
CLKIN
DATAIN
HIZ
Phase Detector &
Loss Of Signal
Circuit
RCLK
RDATA
LOS
PHO
VC
LOSIN
CLK1
VCXO
Divider
OPN
CLK2
Op
Amp
OPOUT
OPP
Ordering Information
PT7V4050
Device Type
16-pin clock recovery module
T
B
C
G
A
51.840 / 25.920
CLK2 Frequency
CLK1 Frequency
Power Supply
A: 5.0V
B: 3.3V
C:
±
20ppm
F:
±
2ppm
G:
±
50ppm
H:
±
100ppm
Frequencies using at CLK1 (MHz)
12.000
16.128
18.432
22.579
28.000
34.368
44.736
51.840
54.000
12.288
13.384
18.936
24.586
30.720
38.880
47.457
65.536
60.000
12.624
16.777
20.000
24.704
32.000
40.000
49.152
19.440
61.440
13.00
16.896
20.480
25.000
32.768
41.2416
49.408
35.328
62.208
16.000
17.920
22.1184
27.000
33.330
41.943
50.000
40.960
62.500
Package Leads
T: Thru-Hole
G: Surface Mount
M: Metal Can
CLK2
A: Divide by 2
B: Divide by 4
C: Divide by 8
D: Divide by 16
Divider
E: Divide by 32
F: Divide by 64
G: Divide by 128
H: Divide by 256
K: Disable
Temperature Range
C: 0
°
C to 70
°
C
T: -40
°
C to 85
°
C
PT0125(07/04)
1
Ver:1
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