S71PL032J80BFW052 datasheet, PDF

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S71PL032J80BFW052: DescriptionMemory Circuit, 2MX16, CMOS, PBGA56, 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56; Categorystorage storage; File Size5MB，188 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/; Environmental Compliance

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S71PL032J80BFW052 Overview

Memory Circuit, 2MX16, CMOS, PBGA56, 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56

S71PL032J80BFW052 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SPANSION
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	56
Reach Compliance Code	compliant
Other features	PSEUDO STATIC RAM IS ORGANIZED AS 512K X 16
JESD-30 code	R-PBGA-B56
JESD-609 code	e1
length	9 mm
memory density	33554432 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	56
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	7 mm
Base Number Matches	1

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S71PL254/127/064/032J based MCPs

Stacked Multi-Chip Product (MCP) Flash Memory and RAM

256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only

Simultaneous Operation Page Mode Flash Memory and

64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static

RAM/Pseudo Static RAM

ADVANCE

Distinctive Characteristics

MCP Features

Power supply voltage of 2.7 to 3.1 volt

High performance

— 55 ns

— 65 ns (65 ns Flash, 70ns pSRAM)

Packages

— 7 x 9 x 1.2mm 56 ball FBGA

— 8 x 11.6 x 1.2mm 64 ball FBGA

— 8 x 11.6 x 1.4mm 84 ball FBGA

Operating Temperature

— –25°C to +85°C

— –40°C to +85°C

General Description

The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages

and consists of:

One or more S29PL (Simultaneous Read/Write) Flash memory die

pSRAM or SRAM

The 256Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2

is used to access the second Flash and no extra address lines are required.

The products covered by this document are listed in the table below:

Flash Memory Density

32Mb

4Mb

8Mb

pSRAM

Density

16Mb

32Mb

64Mb

S71PL032J40

S71PL032J80

S71PL032JA0

S71PL064J80

S71PL064JA0

S71PL064JB0

S71PL127JA0

S71PL127JB0

S71PL127JC0

S71PL254JB0

S71PL254JC0

64Mb

128Mb

256Mb

Flash Memory Density

32Mb

SRAM Density (Note)

4Mb

8Mb

S71PL032J04

S71PL032J08

S71PL064J08

64Mb

Note:

Not recommended for new designs; use pSRAM based MCPs instead.

Publication Number

S71PL254/127/064/032J_00

Revision

Amendment

Issue Date

July 16, 2004

A d v a n c e

I n f o r m a t i o n

S71PL254/127/064/032J based MCPs

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1

MCP Features ........................................................................................................ 1

Table 11. PL032J Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................... 48

Selecting a Sector Protection Mode .............................................................48

Table 12. Sector Protection Schemes ................................... 49

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2

32Mb Flash Memory .............................................................................................2

64Mb Flash Memory .............................................................................................2

128Mb Flash Memory ...........................................................................................2

Persistent Sector Protection . . . . . . . . . . . . . . . . 49

Persistent Protection Bit (PPB) ......................................................................49

Persistent Protection Bit Lock (PPB Lock) .................................................50

Persistent Sector Protection Mode Locking Bit ........................................ 51

Password Protection Mode . . . . . . . . . . . . . . . . . . 51

Password and Password Mode Locking Bit ................................................ 52

64-bit Password .................................................................................................. 52

Write Protect (WP#) ....................................................................................... 53

Persistent Protection Bit Lock ................................................................... 53

High Voltage Sector Protection ..................................................................... 53

Figure 1. In-System Sector Protection/Sector Unprotection

Algorithms........................................................................ 54

Connection Diagram (S71PL032J)

Connection Diagram (S71PL064J)

Connection Diagram (S71PL127J)

Connection Diagram (S71PL254J)

. . . . . . . . . . . . . .8

. . . . . . . . . . . . . .9

. . . . . . . . . . . . . 10

. . . . . . . . . . . . . 11

Special Handling Instructions For FBGA Package .................................. 11

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 13

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 18

TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)

9 x 7mm Package ................................................................................................. 18

TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6mm Package ............................................................................................. 19

FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA)

8 x 11.6mm ............................................................................................................ 20

Temporary Sector Unprotect ........................................................................ 55

Figure 2. Temporary Sector Unprotect Operation ................... 55

SecSi™ (Secured Silicon) Sector Flash Memory Region .......................... 55

Factory-Locked Area (64 words) .............................................................. 55

Customer-Lockable Area (64 words) ...................................................... 56

SecSi Sector Protection Bits ....................................................................... 56

Figure 3. SecSi Sector Protect Verify .................................... 57

S29PL127J/S29PL064J/S29PL032J for MCP

General Description . . . . . . . . . . . . . . . . . . . . . . . 23

Simultaneous Read/Write Operation with Zero Latency ......................23

Page Mode Features ...........................................................................................23

Standard Flash Memory Features ...................................................................23

Hardware Data Protection ............................................................................. 57

Low VCC Write Inhibit ................................................................................ 57

Write Pulse “Glitch” Protection ............................................................... 57

Logical Inhibit ................................................................................................... 57

Power-Up Write Inhibit ............................................................................... 57

Common Flash Memory Interface (CFI) . . . . . . 58

Table 13. CFI Query Identification String .............................. 58

Table 14. System Interface String ........................................ 59

Table 15. Device Geometry Definition ................................... 59

Table 16. Primary Vendor-Specific Extended Query ................ 60

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 25

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Simultaneous Read/Write Block Diagram . . . . . 27

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .29

Table 1. PL127J Device Bus Operations ................................ 29

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 62

Reading Array Data ...........................................................................................62

Reset Command .................................................................................................62

Autoselect Command Sequence .................................................................... 63

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................ 63

Word Program Command Sequence ........................................................... 63

Unlock Bypass Command Sequence ........................................................64

Figure 4. Program Operation ............................................... 65

Requirements for Reading Array Data ........................................................ 29

Random Read (Non-Page Read) ............................................................... 29

Page Mode Read ............................................................................................. 30

Table 2. Page Select .......................................................... 30

Chip Erase Command Sequence ................................................................... 65

Sector Erase Command Sequence ................................................................66

Figure 5. Erase Operation ................................................... 67

Simultaneous Read/Write Operation .......................................................... 30

Table 3. Bank Select .......................................................... 30

Writing Commands/Command Sequences ..................................................31

Accelerated Program Operation ................................................................31

Autoselect Functions ......................................................................................31

Automatic Sleep Mode ......................................................................................32

RESET#: Hardware Reset Pin .........................................................................32

Output Disable Mode ........................................................................................32

Table 4. PL127J Sector Architecture ..................................... 33

Table 5. PL064J Sector Architecture ..................................... 40

Table 6. PL032J Sector Architecture ..................................... 43

Table 7. SecSiTM Sector Addresses ...................................... 44

Autoselect Mode .................................................................................................45

Table 8. Autoselect Codes (High Voltage Method) .................. 45

Table 9. PL127J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 46

Table 10. PL064J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 47

Erase Suspend/Erase Resume Commands .................................................. 67

Password Program Command .......................................................................68

Password Verify Command .............................................................................68

Password Protection Mode Locking Bit Program Command ..............68

Persistent Sector Protection Mode Locking Bit Program

Command .............................................................................................................69

SecSi Sector Protection Bit Program Command ......................................69

PPB Lock Bit Set Command ............................................................................69

DYB Write Command ......................................................................................69

Password Unlock Command ..........................................................................69

PPB Program Command ..................................................................................70

All PPB Erase Command ..................................................................................70

DYB Write Command ......................................................................................70

PPB Lock Bit Set Command ............................................................................70

Command .............................................................................................................. 71

Command Definitions Tables .......................................................................... 71

Table 17. Memory Array Command Definitions ...................... 71

July 16, 2004 S71PL254/127/064/032J_00A3

A d v a n c e

I n f o r m a t i o n

Table 18. Sector Protection Command Definitions .................. 72

Write Operation Status . . . . . . . . . . . . . . . . . . . . 73

DQ7: Data# Polling ............................................................................................73

Figure 6. Data# Polling Algorithm......................................... 74

Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 98

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Power Up ..............................................................................................................99

Figure 23. Power Up 1 (CS1# Controlled) ............................. 99

Figure 24. Power Up 2 (CS2 Controlled)................................ 99

DQ6: Toggle Bit I ................................................................................................75

Figure 7. Toggle Bit Algorithm.............................................. 76

DQ2: Toggle Bit II ...............................................................................................76

Reading Toggle Bits DQ6/DQ2 ......................................................................76

DQ5: Exceeded Timing Limits ........................................................................77

DQ3: Sector Erase Timer .................................................................................77

Table 19. Write Operation Status ......................................... 78

Functional Description . . . . . . . . . . . . . . . . . . . . . 99

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 100

DC Recommended Operating Conditions . . . . . 100

Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . . 100

DC and Operating Characteristics . . . . . . . . . . . 100

Common ............................................................................................................. 100

16M pSRAM ...........................................................................................................101

32M pSRAM ..........................................................................................................101

64M pSRAM .........................................................................................................102

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .79

Figure 8. Maximum Overshoot Waveforms............................. 79

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .80

Industrial (I) Devices ......................................................................................... 80

Extended (E) Devices ........................................................................................ 80

Supply Voltages ................................................................................................... 80

AC Operating Conditions . . . . . . . . . . . . . . . . . . 102

Test Conditions (Test Load and Test Input/Output Reference) ........102

Figure 25. Output Load .................................................... 102

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 20. CMOS Compatible ................................................ 81

AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .82

Test Conditions .................................................................................................. 82

Figure 9. Test Setups......................................................... 82

Table 21. Test Specifications ............................................... 82

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 104

Read Timings .......................................................................................................104

Figure 26. Timing Waveform of Read Cycle(1) ..................... 104

Figure 27. Timing Waveform of Read Cycle(2) ..................... 104

Figure 28. Timing Waveform of Read Cycle(2) ..................... 104

ACC Characteristics (Ta = -40°C to 85°C, V

= 2.7 to 3.1 V) ........103

SWITCHING WAVEFORMS ..........................................................................83

Table 22. KEY TO SWITCHING WAVEFORMS ......................... 83

Figure 10. Input Waveforms and Measurement Levels............. 83

Write Timings .....................................................................................................105

Figure 29. Write Cycle #1 (WE# Controlled)........................

Figure 30. Write Cycle #2 (CS1# Controlled) ......................

Figure 31. Timing Waveform of Write Cycle(3) (CS2

Controlled) .....................................................................

Figure 32. Timing Waveform of Write Cycle(4) (UB#, LB#

Controlled) .....................................................................

105

106

VCC RampRate ...................................................................................................83

Read Operations ................................................................................................ 84

Table 23. Read-Only Operations .......................................... 84

Figure 11. Read Operation Timings ....................................... 84

Figure 12. Page Read Operation Timings ............................... 85

Reset ...................................................................................................................... 85

Table 24. Hardware Reset (RESET#) .................................... 85

Figure 13. Reset Timings..................................................... 86

Erase/Program Operations ............................................................................. 87

Table 25. Erase and Program Operations .............................. 87

Timing Diagrams ................................................................................................. 88

Figure 14. Program Operation Timings .................................. 88

Figure 15. Accelerated Program Timing Diagram .................... 88

Figure 16. Chip/Sector Erase Operation Timings ..................... 89

Figure 17. Back-to-back Read/Write Cycle Timings ................. 89

Figure 18. Data# Polling Timings (During Embedded

Algorithms) ....................................................................... 90

Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 90

Figure 20. DQ2 vs. DQ6 ...................................................... 91

pSRAM Type 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Absolute Maximum Ratings (see Note) . . . . . . . 108

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 30. DC Recommended Operating Conditions ............... 108

Table 31. DC Characteristics (T

= -25°C to 85°C, VDD

= 2.6 to 3.3V) ................................................................. 109

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 32. AC Characteristics and Operating Conditions

= -25°C to 85°C, V

= 2.6 to 3.3V) ............................. 109

Table 33. AC Test Conditions ............................................. 110

Figure 33. AC Test Loads .................................................. 110

Figure 34. State Diagram ................................................. 111

Table 34. Standby Mode Characteristics .............................. 111

Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 26. Temporary Sector Unprotect ................................. 91

Figure 21. Temporary Sector Unprotect Timing Diagram.......... 91

Figure 22. Sector/Sector Block Protect and Unprotect Timing

Diagram............................................................................ 92

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 35. Read Cycle 1—Addressed Controlled ...................

Figure 36. Read Cycle 2—CS1# Controlled..........................

Figure 37. Write Cycle 1—WE# Controlled ..........................

Figure 38. Write Cycle 2—CS1# Controlled .........................

Figure 39. Write Cycle3—UB#, LB# Controlled ....................

Figure 40. Deep Power-down Mode ....................................

Figure 41. Power-up Mode ................................................

Figure 42. Abnormal Timing ..............................................

111

112

113

114

Controlled Erase Operations ..........................................................................93

Table 27. Alternate CE# Controlled Erase and Program

Operations ....................................................................... 93

Table 28. Alternate CE# Controlled Write (Erase/Program)

Operation Timings ............................................................. 94

Table 29. Erase And Programming Performance .................... 95

BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 95

Type 2 pSRAM

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Product Information . . . . . . . . . . . . . . . . . . . . . . . 97

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

pSRAM Type 6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

S71PL254/127/064/032J_00A3 July 16, 2004

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