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TEMPFET
®
BTS 131
Features
q
q
q
q
q
N channel
Logic level
Enhancement mode
Temperature sensor with thyristor characteristic
The drain pin is electrically shorted to the tab
1
2
3
Pin
1
G
2
D
3
S
Type
BTS 131
V
DS
50 V
I
D
25 A
R
DS(on)
0.06
Ω
Package
TO-220AB
Ordering Code
C67078-A5002-A4
Maximum Ratings
Parameter
Drain-source voltage
Drain-gate voltage,
R
GS
= 20 kΩ
Gate-source voltage
Continuous drain current,
T
C
= 25
°C
ISO drain current
T
C
= 85 ˚C,
V
GS
= 10 V,
V
DS
= 0.5 V
Pulsed drain current,
Short circuit current,
Symbol
Values
50
50
±
10
25
6.5
100
80
1200
75
– 55 ... + 150
E
55/150/56
K/W
≤
1.67
≤
75
°C
–
W
A
Unit
V
V
DS
V
DGR
V
GS
I
D
I
D-ISO
I
D puls
I
SC
P
SCmax
P
tot
T
j
,
T
stg
–
–
T
C
= 25
°C
T
j
= – 55 ... + 150
°C
Short circuit dissipation,
T
j
= – 55 ... + 150
°C
Power dissipation
Operating and storage temperature range
DIN humidity category, DIN 40 040
IEC climatic category, DIN IEC 68-1
Thermal resistance
Chip-case
Chip-ambient
1
R
th JC
R
th JA
1
19.02.04
TEMPFET
®
BTS 131
Electrical Characteristics
at
T
j
= 25
°C,
unless otherwise specified.
Parameter
Symbol
min.
Static Characteristics
Drain-source breakdown voltage
V
GS
= 0
, I
D
= 0.25 mA
Gate threshold voltage
V
GS
=
V
DS
, I
D
= 1 mA
Zero gate voltage drain current
V
GS
= 0 V,
V
DS
= 50 V
T
j
= 25
°C
T
j
= 125
°C
Gate-source leakage current
V
GS
= 20 V,
V
DS
= 0
T
j
= 25
°C
T
j
= 150
°C
Drain-source on-state resistance
V
GS
= 4.5 V
, I
D
=12 A
Dynamic Characteristics
Forward transconductance
V
DS
≥
2
×
I
D
×
R
DS(on)max
,
I
D
= 12 A
Input capacitance
V
GS
= 0
, V
DS
= 25 V,
f
= 1 MHz
Output capacitance
V
GS
= 0
, V
DS
= 25 V,
f
= 1 MHz
Reverse transfer capacitance
V
GS
= 0
, V
DS
= 25 V,
f
= 1 MHz
Turn-on time
t
on
, (
t
on
=
t
d(on)
+
t
r
)
V
CC
= 30 V,
V
GS
= 5 V,
I
D
= 3 A,
R
GS
= 50
Ω
Turn-off time
t
off
, (
t
off
=
t
d(off)
+
t
f
)
V
CC
= 30 V,
V
GS
= 5 V,
I
D
= 3 A,
R
GS
= 50
Ω
Values
typ.
max.
Unit
V
(BR)DSS
50
–
2.0
–
2.5
V
V
GS(th)
1.5
I
DSS
–
–
1
100
10
300
µA
I
GSS
–
–
10
2
0.05
100
4
0.06
nA
µA
Ω
–
R
DS(on)
g
fs
12
17
1050
500
200
25
60
100
75
22
S
pF
800
1400
750
300
40
90
130
95
ns
C
iss
C
oss
–
C
rss
–
t
d(on)
t
r
t
d(off)
t
f
–
–
–
–
2
19.02.04
FPGA/CPLD
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