K8F12(13)15ET(B)M
NOR FLASH MEMORY
512Mb M-die MLC NOR Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.2
September, 2006
K8F12(13)15ET(B)M
NOR FLASH MEMORY
Document Title
512M Bit (32M x16) Muxed Burst , Multi Bank MLC NOR Flash Memory
Revision History
Revision No. History
0.0
0.1
Initial
Draft Date
October 20, 2005
Remark
Advance
Advance
Revision
October 28, 2005
- Correct Icc2(Active Write Current) from 15mA(min), 30mA(max)
to 25mA(typ), 40mA(max)
- Correct default value of programmable wait state from A11~A14
"1010"(Data valid on the 14th active CLK) to "1011"(Data valid on the
15th active CLK)
- Correct the description of Figure 4(Continuous Burst Mode
Read@133MHz) for exact explanation of initial access time.
- Correct the description of Figure 5(Continuous Burst Mode
Read@108MHz) for exact explanation of initial access time.
- Correct the description of Figure 6(8 word Linear Burst Mode with
Wrap Around@133MHz) for exact explanation of initial access time.
- Correct the description of Figure 7(8 word Linear Burst with RDY Set
One Cycle Before Data) for exact explanation of initial access time.
- Correct tBA(Burst Access Time Valid Clock to Output Delay)
from 8ns(@83Mhz) to 9ns(@83MHz)
- Correct tBDH(Data Hold Time from Next Clock Cycle) from
4ns(@66MHz), 2.25ns(@108MHz), 1.5ns(@133MHz) to
3ns(@66MHz), 2ns(@108MHz), 2ns(@133MHz)
- Correct tRDYA(Clock to RDY Setup Time) from 8ns(@83Mhz) to
9ns(@83MHz)
- Correct tRDYS(RDY setup to Clock) from 4ns(@66MHz),
2.25ns(@108MHz), 1.5ns(@133MHz) to 3ns(@66MHz),
2ns(@108MHz), 2ns(@133MHz)
- Correct typo
0.2
- Correct typo
December 20, 2005 Advance
- Modify figures for first word boundary crossing
- Modify output driver setting table
- Change tAVDH(AVD Hold Time from CLK) from 6ns(@66MHz),
5ns(@83MHz) to 2ns(@66/83MHz)
- Changes tAAVDH(Address Hold Time from Rising Egde of AVD)
from 7ns(@66MHz), 5ns(@83MHz) to 2ns(@66/83MHz)
- Change tCES(CE Setup Time to CLK) from 4.5ns @133MHz to 6ns
@133MHz
- Add Ordering Information for Density
12 : 512Mb for 66/83MHz, 13 : 512Mb for 108/133Mhz
- Add Product Classification Table (Table 1-1)
- CFI note is added (Max Operation frequency : Data 53H is in 66/
83Mhz part
- Correct typo
- Specification is finalized
April 04, 2006
Advance
0.3
1.0
June 08, 2006
1.1
Active Asynchronous read Current(@1Mhz) is changed
September 08, 2006
3mA(typ.),5mA(max.) to 8mA(typ.), 10mA(max.)
'In erase/program suspend followed by resume operation, min. 200ns
is needed for checking the busy status' is added
- Frequency information is added to Programmable Wait State at
Burst Mode Configuration Register Table.
- "Asynchronous mode may not support read following four sequential
invalid read condition within 200ns." is added
2
Revision 1.2
September, 2006
K8F12(13)15ET(B)M
Revision No. History
1.2
Correct typo
NOR FLASH MEMORY
Draft Date
September 28, 2006
Remark
3
Revision 1.2
September, 2006
K8F12(13)15ET(B)M
NOR FLASH MEMORY
512M Bit (32M x16) Muxed Burst , Multi Bank MLC NOR Flash Memory
FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 33,554,432 x 16 bit ( Word Mode Only)
•
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (32Mb Partition)
•
OTP Block : Extra 512-Word block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time : 110ns
- Synchronous Random Access Time :110ns
- Burst Access Time :
11ns (66MHz) / 9ns (83MHz) / 7ns (108MHz) / 6ns (133MHz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
•
Block Architecture
- Four 16Kword blocks and five hundred eleven 64Kword blocks
- Bank 0 contains four 16 Kword blocks and thirty-one 64Kword
blocks
- Bank 1 ~ Bank 15 contain four hundred eighty 64Kword blocks
•
Reduce program time using the V
PP
•
Support 32 words Buffer Program
•
Power Consumption (Typical value, C
L
=30pF)
- Synchronous Read Current : 35mA at 133MHz
- Program/Erase Current : 25mA
- Read While Program/Erase Current : 45mA
- Standby Mode/Auto Sleep Mode : 30uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
100K Program/Erase Cycles Minimum
•
Data Retention : 10 years
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Output Driver Control by Configuration Register
•
Package : 64 - ball FBGA Type (9mm x 11mm),
0.5 mm ball pitch,
1.0mm (Max.) Thickness
GENERAL DESCRIPTION
The K8F12(13)15E featuring single 1.8V power supply is a
512Mbit Muxed Burst Multi Bank Flash Memory organized as
32Mx16. The memory architecture of the device is designed to
divide its memory arrays into 515 blocks with independent hard-
ware protection. This block architecture provides highly flexible
erase and program capability. The K8F12(13)15E NOR Flash
consists of sixteen banks. This device is capable of reading
data from one bank while programming or erasing in the other
bank.
Regarding read access time, the K8F1215E provides an 11ns
burst access time and an 110ns initial access time at 66MHz. At
83MHz, the K8F1215E provides an 9ns burst access time and
an 110ns initial access time. At 108MHz, the K8F1315E pro-
vides an 7ns burst access time and an 110ns initial access time.
At 133MHz, the K8F1315E provides an 6ns burst access time
and an 110ns initial access time. The device performs a pro-
gram operation in units of 16 bits (Word) and erases in units of a
block. Single or multiple blocks can be erased. The block erase
operation is completed within typically 0.6sec. The device
requires 25mA as program/erase current in the extended tem-
perature ranges.
The K8F12(13)15E NOR Flash Memory is created by using
Samsung's advanced CMOS process technology. This device is
available in 64ball FBGA package.
PIN DESCRIPTION
Pin Name
A16 - A24
Pin Function
Address Inputs
A/DQ0 - A/DQ15 Multiplexed Address/Data input/output
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
DPD
Vcc
V
SS
Chip Enable
Output Enable
Hardware Reset
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Deep Power Down
Power Supply
Ground
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
4
Revision 1.2
September, 2006
K8F12(13)15ET(B)M
64 Ball FBGA TOP VIEW (BALL DOWN)
NOR FLASH MEMORY
1
2
3
4
5
6
7
8
9
10
A
DNU
DNU
V
SS
A24
V
CC
Vss
Vcc
DNU
DNU
DNU
B
RDY
A21
V
SS
CLK
V
CC
WE
V
PP
A19
A17
A22
C
Vccq
A16
A20
AVD
A23
RESET
WP
A18
CE
Vssq
D
Vssq
A/DQ7
A/DQ6
A/DQ13
A/DQ12
A/DQ3
A/DQ2
A/DQ9
A/DQ8
OE
E
A/DQ15
A/DQ14
Vssq
A/DQ5
A/DQ4
A/DQ11
A/DQ10
Vccq
A/DQ1
A/DQ0
F
DNU
DNU
DNU
Vccq
Vssq
DPD
Vccq
DNU
DNU
DNU
FUNCTIONAL BLOCK DIAGRAM
Bank 0
Address
Vcc
Vss
Vpp
CLK
CE
OE
WE
WP
RESET
RDY
AVD
DPD
I/O
Interface
&
Bank
Control
Bank 1
Address
X
Dec
X
Dec
Bank 0
Cell Array
Y Dec
Latch &
Control
Y Dec
Bank 1
Cell Array
Latch &
Control
Bank 15
Address
X
Dec
Bank 15
Cell Array
Y Dec
A16~A24
A/DQ0~
A/DQ15
Erase
Control
Block
Inform
Program
Control
Latch &
Control
High
Voltage
Gen.
5
Revision 1.2
September, 2006
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