5962-9754502QXA datasheet, PDF

Datasheet> All Categories > storage> storage> 5962-9754502QXA

5962-9754502QXA: DescriptionSynchronous DRAM, 1MX16, 20ns, CMOS, CDFP50, CERAMIC, DFP-50; Categorystorage storage; File Size539KB，51 Pages; ManufacturerMicross; Websitehttps://www.micross.com

Download Datasheet Parametric Compare View All

5962-9754502QXA Overview

Synchronous DRAM, 1MX16, 20ns, CMOS, CDFP50, CERAMIC, DFP-50

5962-9754502QXA Parametric

Parameter Name	Attribute value
Parts packaging code	DFP
package instruction	DFP, FL50,.67,32
Contacts	50
Reach Compliance Code	compli
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	20 ns
Other features	AUTO REFRESH
Maximum clock frequency (fCLK)	50 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-CDFP-F50
JESD-609 code	e0
length	21 mm
memory density	16777216 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	50
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1MX16
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL50,.67,32
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	3.3 V
Certification status	Qualified
refresh cycle	4096
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	3.55 mm
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.002 A
Maximum slew rate	0.15 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	0.8 mm
Terminal location	DUAL
width	16.5 mm
Base Number Matches	1

Preview

Download Datasheet

View All

REVISIONS

LTR

DESCRIPTION

Updated boilerplate. Added device type 03 to drawing. Changed t

APW

minimum

limits from 75ns and 100 ns to the quantity t

+ t

. Removed all references to

BSD

from drawing. - glg

Changes in accordance with NOR 5962-R071-98. - glg

Changes to paragraph 1.3 and 1.4. Table IA changes to I

, I

CC2N

, I

CC3P

CC3PS

, I

CC3N

, I

CC4

, and I

CC5

. Removed number of cycles table from Table IA,

sheet 12. - glg

Change CAGE code to correct CAGE of 67268. Update to current boilerplate.

Editorial changes throughout. - gap

DATE (YR-MO-DA)

98-01-20

APPROVED

Raymond Monnin

98-03-19

99-03-16

Raymond Monnin

02-04-02

Raymond Monnin

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Gary L. Gross

CHECKED BY

Jeff Bowling

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216

http://www.dscc.dla.mil

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY All DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

APPROVED BY

Raymond Monnin

DRAWING APPROVAL DATE

97-06-17

REVISION LEVEL

MICROCIRCUIT, MEMORY, DIGITAL, CMOS,

512K x 16-BIT x 2-BANK, SYNCHRONOUS

DYNAMIC RANDOM ACCESS MEMORY (SDRAM),

MONOLITHIC SILICON

SIZE

SHEET

1 OF

5962-E310-02

CAGE CODE

67268

5962-97545

DSCC FORM 2233

APR 97

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

HANDBOOKS

DEPARTMENT OF DEFENSE

MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's).

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with MIL-

PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes N, Q, and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth tables. The truth tables shall be as specified on figure 3.

3.2.4 Output load circuit. The output load circuit shall be as specified on figure 4.

3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5.

3.2.6 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns

cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be

allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the

manufacturer and shall be made available to the preparing or aquiring activity upon request. For device class Q and V,

alternate test patterns shall be under the control of the device manufacturer’s Technology Review Board (TRB) in accordance

with MIL-PRF-38535 and shall be made available to the preparing or aquiring activity upon request.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

ambient operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space

limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the

RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535.

Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

SIZE

REVISION LEVEL

5962-97545

SHEET

DSCC FORM 2234

APR 97

3.5.1 Certification/compliance mark. The certification mark for device classes N, Q, and V shall be a "QML" or "Q" as

required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix

3.6 Certificate of compliance. For device classes N, Q, and V, a certificate of compliance shall be required from a

QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a

certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-

HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of

supply for this drawing shall affirm that the manufacturer's product meets, for device classes N, Q, and V, the requirements of

MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes N, Q, and V in MIL-PRF-38535 or

for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain

the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 41 (see MIL-PRF-38535, appendix A).

4. QUALITY ASSURANCE PROVISIONS

4.1 Sampling and inspection. For device classes N, Q, and V, sampling and inspection procedures shall be in accordance

with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM

plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall

be in accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes N, Q, and V, screening shall be in accordance with MIL-PRF-38535, and shall be

conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be

in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance

inspection.

4.2.1 Additional criteria for device class M.

Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)

electrical parameters of method 5004 and substitute lines 1 through 6 of table II herein.

The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,

and power dissipation, as applicable, in accordance with the intent specified in test method 1015.

(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).

Interim and final electrical parameters shall be as specified in table II herein.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

SIZE

REVISION LEVEL

5962-97545

SHEET

DSCC FORM 2234

APR 97

5962-9754502QXA Related Products

	5962-9754502QXA	5962-9754503QXA	5962-9754501QXA
Description	Synchronous DRAM, 1MX16, 20ns, CMOS, CDFP50, CERAMIC, DFP-50	Synchronous DRAM, 1MX16, 12ns, CMOS, CDFP50, CERAMIC, DFP-50	Synchronous DRAM, 1MX16, 15ns, CMOS, CDFP50, CERAMIC, DFP-50
Parts packaging code	DFP	DFP	DFP
package instruction	DFP, FL50,.67,32	DFP, FL50,.67,32	DFP, FL50,.67,32
Contacts	50	50	50
Reach Compliance Code	compli	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	20 ns	12 ns	15 ns
Other features	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH
Maximum clock frequency (fCLK)	50 MHz	83 MHz	66 MHz
I/O type	COMMON	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 code	R-CDFP-F50	R-CDFP-F50	R-CDFP-F50
JESD-609 code	e0	e0	e0
length	21 mm	21 mm	21 mm
memory density	16777216 bi	16777216 bit	16777216 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	16	16	16
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	50	50	50
word count	1048576 words	1048576 words	1048576 words
character code	1000000	1000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C
organize	1MX16	1MX16	1MX16
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DFP	DFP
Encapsulate equivalent code	FL50,.67,32	FL50,.67,32	FL50,.67,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK
power supply	3.3 V	3.3 V	3.3 V
Certification status	Qualified	Qualified	Qualified
refresh cycle	4096	4096	4096
Filter level	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q
Maximum seat height	3.55 mm	3.55 mm	3.55 mm
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.002 A	0.002 A	0.002 A
Maximum slew rate	0.15 mA	0.18 mA	0.175 mA
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	FLAT	FLAT	FLAT
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL
width	16.5 mm	16.5 mm	16.5 mm
Base Number Matches	1	1	1

Recommended Resources

Typical electronic rodent killer circuit diagram

Ringtone control circuit

Voltage dividing self-bias circuit

LT1086 application circuit diagram

Small battery charger with selectable charging time

Computer motherboard circuit diagram 815 3_03

I don't understand many formulas, and my head is buzzing.: How is the formula for the red line calculated? Why is the result 5.62A? I can't get this result no matter how I calculate it....; sky999 PCB Design

Continued from the previous post - MAGTROL HD-106-8NA-0100 dynamometer failure: The figure shows the fault display phenomenon of the control display DSP6001 of the MAGTROL HD-106-8NA-0100 dynamometer, which is over-range. The maximum range of the machine is 18mNm (about 183.78g.c...; UUC Industrial Control Electronics

Why does the keilc debugger jump to a sub-function that has not been called when running the main function?: Why does the keilc debugger jump to a sub-function that has not been called when running the main function? After putting that sub-function in the main function, the main function will run to a part a...; 一脸懵逼 MCU

A design about single chip microcomputer: The content is as follows: 1. Through the serial port, prompt the user to enter the countdown time (0~999 seconds); 2. After the time setting is completed, prompt the user to select the control mode: ...; kkhtkkht Embedded System

Voice recognition chip: I want to study voice recognition recently, but I don't know which voice chip is better, especially for non-specific speech recognition. How about Lingyang SPCE061a? Please give me some advice!...; hmzhb Embedded System

About 2812 and LCD: Has anyone used 2812 to display real-time waveforms on an LCD screen? I am currently using sed1335 as the LCD driver chip. Now, there is a problem: when I am drawing a line, the screen will not displa...; ATT001 Microcontroller MCU

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components