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MO9122DB6-D0K-25S0-0220123456T

Description
LVDS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size595KB,8 Pages
ManufacturerDaishinku Corp.
Websitehttp://www.kds.info/
Environmental Compliance
Download Datasheet Parametric View All

MO9122DB6-D0K-25S0-0220123456T Overview

LVDS Output Clock Oscillator,

MO9122DB6-D0K-25S0-0220123456T Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid7206779856
Reach Compliance Codeunknown
Other featuresSTANDBY; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR
maximum descent time0.6 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
Installation featuresSURFACE MOUNT
Nominal operating frequency220.123456 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
Oscillator typeLVDS
Output load100 OHM
physical size5.0mm x 3.2mm x 0.75mm
longest rise time0.6 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
MO9122
220-625 MHz High Performance Differential Oscillator
Features
Applications
Any frequency between 220 MHz and 625 MHz accurate to 6 decimal
places
LVPECL and LVDS output signaling types
0.6ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Frequency stability as low as ±10 ppm
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2x2.5, 5.0x3.2 and 7.0x5.0 mmxmm
For frequencies lower than 220 MHz, refer to MO9121 datasheet
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,
PCI-Express
networking, instrumentation, storage, servers

Telecom,
Electrical Characteristics
Parameter and Conditions
Symbol
Min.
Typ.
Max.
Unit
Condition
LVPECL and LVDS, Common Electrical Characteristics
+2.97
Supply Voltage
Output Frequency Range
Vdd
f
+2.25
+2.25
220
-10
Frequency Stability
F_stab
-20
-25
-50
First Year Aging
10-year Aging
Operating Temperature Range
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Start-up Time
Resume Time
Duty Cycle
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
F_aging1
F_aging10
T_use
VIH
VIL
Z_in
T_start
T_resume
DC
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_jitt
-2.0
-5.0
-40
-20
70%
2.0
45
Vdd-1.1
Vdd-1.9
+1.2
RMS Phase Jitter (random)
T_phj
+3.3
+2.5
100
6.0
6.0
+61
+1.6
300
1.2
1.2
1.2
0.6
+3.63
+2.75
+3.63
625
+10
+20
+25
+50
+2.0
+5.0
+85
+70
30%
250
10
10
55
+69
+35
+1.0
+100
+30
Vdd-0.7
Vdd-1.5
+2.0
500
115
1.7
1.7
1.7
0.85
V
V
V
MHz
ppm
ppm
ppm
ppm
ppm
ppm
°C
°C
Vdd
Vdd
ms
ms
%
mA
mA
μA
μA
mA
V
V
V
Ps
Ns
Ps
Ps
Ps
Ps
+25°C
+25°C
Industrial
Extended
ST
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time
ST
pin
crosses 50% threshold.
Contact KDS for tighter duty cycle
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST
= Low, for all Vdds
Termination schemes in Figures 1 and 2 - XX ordering code
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
LVPECL, DC and AC Characteristics
Maximum average current drawn from OUT+ or OUT-
See Figure 1(a)
See Figure 1(a)
See Figure 1(b)
20% to 80%, see Figure 1(a)
f = 220 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 266 MHz, Vdd = +3.3V or +2.5V
f = 312.5 MHz, Vdd = +3.3V or +2.5V
f = 622.08 MHz, Vdd = +3.3V or +2.5V
f = 312.5 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Excluding Load Termination Current, Vdd = +3.3V or +2.5V
OE = Low
See Figure 2
LVDS, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Differential Output Voltage
Idd
I_OE
VOD
+250
+47
+350
+55
+35
+450
mA
mA
mV
Daishinku Corp.
Rev. 1.05
1389 Shinzaike, Hiraoka-cho, Kakogawa, Hyogo 675-0194 Japan
+81-79-426-3211
www.kds.info
Revised October 6, 2014

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