54ACT112FMQB datasheet, PDF - EEWORLD Datasheet

54ACT112FMQB: DescriptionIC ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERPACK-16, FF/Latch; Categorylogic logic; File Size348KB，8 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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54ACT112FMQB Overview

IC ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERPACK-16, FF/Latch

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	National Semiconductor（TI ）
package instruction	CERPACK-16
Reach Compliance Code	unknown
series	ACT
JESD-30 code	R-GDFP-F16
JESD-609 code	e0
length	9.6645 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
MaximumI(ol)	0.024 A
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DFP
Encapsulate equivalent code	FL16,.3
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
propagation delay (tpd)	14 ns
Certification status	Not Qualified
Filter level	MIL-STD-883 Class B
Maximum seat height	2.032 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	6.604 mm
minfmax	80 MHz
Base Number Matches	1

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