82V3380DQ datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> 82V3380DQ

82V3380DQ: DescriptionTelecom Circuit, 1-Func, CMOS, PQFP100, TQFP-100; CategoryWireless rf/communication Telecom circuit; File Size1MB，170 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric Compare View All

82V3380DQ Overview

Telecom Circuit, 1-Func, CMOS, PQFP100, TQFP-100

82V3380DQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	1.4 mm
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

Preview

Download Datasheet

View All

SYNCHRONOUS ETHERNET

WAN PLL

IDT82V3380

Version 1

October 20, 2008

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

FEATURES .............................................................................................................................................................................. 9

HIGHLIGHTS.................................................................................................................................................................................................... 9

MAIN FEATURES ............................................................................................................................................................................................ 9

OTHER FEATURES ......................................................................................................................................................................................... 9

APPLICATIONS....................................................................................................................................................................... 9

DESCRIPTION....................................................................................................................................................................... 10

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11

1 PIN ASSIGNMENT ........................................................................................................................................................... 12

2 PIN DESCRIPTION .......................................................................................................................................................... 13

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 19

RESET ........................................................................................................................................................................................................... 19

MASTER CLOCK .......................................................................................................................................................................................... 19

INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 20

3.3.1 Input Clocks .................................................................................................................................................................................... 20

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 20

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 21

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 23

3.5.1 LOS Monitoring .............................................................................................................................................................................. 23

3.5.2 Activity Monitoring ......................................................................................................................................................................... 23

3.5.3 Frequency Monitoring ................................................................................................................................................................... 24

3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 25

3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 25

3.6.2 Forced Selection ............................................................................................................................................................................ 26

3.6.3 Automatic Selection ....................................................................................................................................................................... 26

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 27

3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 27

3.7.1.1 Fast Loss .......................................................................................................................................................................... 27

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 27

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 27

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 27

3.7.2 Locking Status ............................................................................................................................................................................... 27

3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 28

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 29

3.8.1 Input Clock Validity ........................................................................................................................................................................ 29

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 29

3.8.2.1 Revertive Switch ............................................................................................................................................................... 29

3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 30

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 30

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 31

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31

3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 33

3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 34

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 34

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 34

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 34

3.10.1.3 Locked Mode .................................................................................................................................................................... 34

3.1

3.2

3.3

Table of Contents

October 20, 2008

IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

3.17

4.1

5.1

5.2

5.3

5.4

5.5

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34

3.10.1.5 Holdover Mode ................................................................................................................................................................. 34

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35

3.10.1.5.4 Manual ........................................................................................................................................................... 35

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35

3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35

3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35

3.10.2.2 Locked Mode .................................................................................................................................................................... 35

3.10.2.3 Holdover Mode ................................................................................................................................................................. 35

T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 37

3.11.1 PFD Output Limit ............................................................................................................................................................................ 37

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37

3.11.3 PBO (T0 only) ................................................................................................................................................................................. 37

3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 37

3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 37

3.11.5.1 T0 Path ............................................................................................................................................................................. 37

3.11.5.2 T4 Path ............................................................................................................................................................................. 38

T0 / T4 APLL ................................................................................................................................................................................................. 39

OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 39

3.13.1 Output Clocks ................................................................................................................................................................................. 39

3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 44

MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 46

INTERRUPT SUMMARY ............................................................................................................................................................................... 47

T0 AND T4 SUMMARY ................................................................................................................................................................................. 47

POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 48

MASTER / SLAVE APPLICATION ............................................................................................................................................................... 49

4 TYPICAL APPLICATION ................................................................................................................................................. 49

5 MICROPROCESSOR INTERFACE .................................................................................................................................. 50

EPROM MODE .............................................................................................................................................................................................. 51

MULTIPLEXED MODE .................................................................................................................................................................................. 52

INTEL MODE ................................................................................................................................................................................................. 54

MOTOROLA MODE ...................................................................................................................................................................................... 56

SERIAL MODE .............................................................................................................................................................................................. 58

6 JTAG ................................................................................................................................................................................ 60

7 PROGRAMMING INFORMATION .................................................................................................................................... 61

7.1

7.2

REGISTER MAP ............................................................................................................................................................................................ 61

REGISTER DESCRIPTION ........................................................................................................................................................................... 67

7.2.1 Global Control Registers ............................................................................................................................................................... 67

7.2.2 Interrupt Registers ......................................................................................................................................................................... 76

7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 81

7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 104

7.2.5 T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 118

7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 122

7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 124

7.2.8 Output Configuration Registers .................................................................................................................................................. 138

7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 148

7.2.10 Synchronization Configuration Registers ................................................................................................................................. 150

JUNCTION TEMPERATURE ...................................................................................................................................................................... 151

8 THERMAL MANAGEMENT ........................................................................................................................................... 151

8.1

Table of Contents

October 20, 2008

IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 152

9.1

9.2

9.3

8.2

8.3

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 151

HEATSINK EVALUATION .......................................................................................................................................................................... 151

9.4

9.5

9.6

9.7

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 152

RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 152

I/O SPECIFICATIONS ................................................................................................................................................................................. 153

9.3.1 AMI Input / Output Port ................................................................................................................................................................ 153

9.3.1.1 Structure ......................................................................................................................................................................... 153

9.3.1.2 I/O Level ......................................................................................................................................................................... 153

9.3.1.3 Over-Voltage Protection ................................................................................................................................................. 155

9.3.2 CMOS Input / Output Port ............................................................................................................................................................ 155

9.3.3 PECL / LVDS Input / Output Port ................................................................................................................................................ 156

9.3.3.1 PECL Input / Output Port ................................................................................................................................................ 156

9.3.3.2 LVDS Input / Output Port ................................................................................................................................................ 158

JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 159

OUTPUT WANDER GENERATION ............................................................................................................................................................ 162

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 163

OUTPUT CLOCK TIMING ........................................................................................................................................................................... 164

ORDERING INFORMATION .......................................................................................................................................... 170

Table of Contents

October 20, 2008

82V3380DQ Related Products

	82V3380DQ	82V3380DQG	82V3380DQG8	82V3380PF
Description	Telecom Circuit, 1-Func, CMOS, PQFP100, TQFP-100	Telecom Circuit, 1-Func, CMOS, PQFP100, GREEN TQFP-100	Clock Generator	Telecom Circuit, 1-Func, CMOS, PQFP100, TQFP-100
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
package instruction	TQFP-100	LFQFP,	,	TQFP-100
Reach Compliance Code	not_compliant	unknown	unknown	not_compliant
Parts packaging code	QFP	QFP	-	QFP
Contacts	100	100	-	100
JESD-30 code	S-PQFP-G100	S-PQFP-G100	-	S-PQFP-G100
length	14 mm	14 mm	-	14 mm
Number of functions	1	1	-	1
Number of terminals	100	100	-	100
Maximum operating temperature	85 °C	85 °C	-	85 °C
Minimum operating temperature	-40 °C	-40 °C	-	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	-	LFQFP
Package shape	SQUARE	SQUARE	-	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	-	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	1.4 mm	1.4 mm	-	1.4 mm
Nominal supply voltage	3.3 V	3.3 V	-	3.3 V
surface mount	YES	YES	-	YES
technology	CMOS	CMOS	-	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	-	TELECOM CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL
Terminal form	GULL WING	GULL WING	-	GULL WING
Terminal pitch	0.5 mm	0.5 mm	-	0.5 mm
Terminal location	QUAD	QUAD	-	QUAD
width	14 mm	14 mm	-	14 mm

Recommended Resources

Equal loudness control circuit

Transformer tap regulator

Triangle gas water heater circuit diagram

Double conversion UPS with output transformer

How the infrared remote control mouse works

A 2.7-inch LCD screen has only 8 data PINs. How should the hardware be connected to use it on a 6410 (ARM11, 32-bit) platform?: A 2.7-inch LCD screen has only 8 data PINs. How should the hardware be connected to use it on a 6410 (ARM11, 32-bit) platform? Should the 8 data PINs of the LCD screen be connected to [7:0] [15:0] [23...; 张皓翔 ARM Technology

Is there anyone who can do this project and develop software similar to FastCAM?: Is there anyone who can do this project to develop software similar to FastCAM, that is, to develop drawing (CAD) and nesting functions similar to FastCAM? If anyone can do it, please contact me immed...; 1581582 Embedded System

【GD32450I-EVAL】+ 05FreeRTOS porting and task creation: [i=s]This post was last edited by DDZZ669 on 2020-9-26 15:34[/i]FreeRTOS is a mini real-time operating system kernel. As a lightweight operating system, its functions include: task management, time ma...; DDZZ669 GD32 MCU

SIM300 GPRS Internet connection failed: I am now using sim300 gprs at command to access the Internet. The command sending process is as follows: AT+CGATT=1 OK AT+CGATT? +CGATT:1 OK AT+CGDCONT=1,"IP","CMNET" OK AT+CGDCONT? +CGDCONT:1,"IP","C...; fefwfWF Embedded System

I would like to ask: What information should I read before developing USB drivers and user programs for XP on a PC? What software should I use for development?: I am a newbie and just received a project: to make a USB driver for XP on a PC. The USB device is made in-house and the driver is also fixed....; smjacky Embedded System

Surveillance Camera Market Application Analysis: [size=14px] Keywords: [b]Surveillance cameras[/b] In the past, surveillance cameras were mainly used for security. With the development of information and network technology and the need for administr...; gzycxfj Industrial Control Electronics

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components