500P04B273ZJ4C datasheet, PDF - EEWORLD Datasheet

500P04B273ZJ4C: DescriptionCeramic Capacitor, Ceramic, 50V, 80% +Tol, 20% -Tol, BX, -/+15ppm/Cel TC, 0.027uF, 3944,; CategoryPassive components capacitor; File Size836KB，6 Pages; ManufacturerJohanson Dielectrics

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500P04B273ZJ4C Overview

Ceramic Capacitor, Ceramic, 50V, 80% +Tol, 20% -Tol, BX, -/+15ppm/Cel TC, 0.027uF, 3944,

Parameter Name	Attribute value
Objectid	864184324
package instruction	, 3944
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	6.5
capacitance	0.027 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	6.477 mm
JESD-609 code	e0
length	9.843 mm
negative tolerance	20%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package form	SMT
positive tolerance	80%
Rated (DC) voltage (URdc)	50 V
series	P(SMT)
size code	3944
Temperature characteristic code	BX
Temperature Coefficient	15% ppm/°C
Terminal surface	Tin/Lead (Sn60Pb40)
width	11.176 mm

FPGA code question?: When defining: reg[2:0] k1; reg[2:0] k2; then wire[2:0] ld = k1[2:0]( ~k2[2:0]); and wire[2:0] ld = k1( ~k2); is there any difference? Can anyone explain it to me? Thanks....; 517596037 FPGA/CPLD

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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