Application Note
DA1469x Application Hardware
Design Guidelines
AN-B-066
Abstract
This document provides the minimal reference schematic, circuit explanation, and design guidelines
for BLE applications based on the SoC of DA1469x family.
AN-B-066
DA1469x Application Hardware Design Guidelines
Contents
Abstract ................................................................................................................................................ 1
Contents ............................................................................................................................................... 2
Figures .................................................................................................................................................. 3
Tables ................................................................................................................................................... 4
1
2
3
4
5
Terms and Definitions................................................................................................................... 5
References ..................................................................................................................................... 5
Introduction.................................................................................................................................... 6
Device Revision Numbering and Marking .................................................................................. 8
Minimal Design for DA1469x SoC ................................................................................................ 8
5.1 Power Section of DA1469x ................................................................................................. 12
5.1.1
Supplying External Loads .................................................................................... 16
5.1.2
Supplying DA1469x at VBAT Voltages At 3 V or Below...................................... 16
5.2 Reset Pin (RSTn) ................................................................................................................ 17
5.3 Digital I/O Pins .................................................................................................................... 17
5.3.1
Interference to XTAL32MHz from GPIOs ............................................................ 18
5.4 Crystals and Clocks ............................................................................................................ 20
5.4.1
32 MHz Clock ...................................................................................................... 21
5.4.2
32.768 kHz Clock................................................................................................. 22
5.4.2.1
Providing DA1469x with a 32.768 kHz Square Wave Clock ........... 23
5.4.3
Generating a Clock Output from DA1469x .......................................................... 24
5.5 UART................................................................................................................................... 27
5.6 SWD (JTAG) ....................................................................................................................... 27
5.7 QSPI FLASH Memory ......................................................................................................... 27
5.8 QSPI RAM Memory............................................................................................................. 28
5.9 USB and VBUS ................................................................................................................... 29
5.9.1
USB ESD Measures ............................................................................................ 29
5.9.2
VBUS Circuitry ..................................................................................................... 30
5.9.3
Over Voltage Protection Circuit (OVP) ................................................................ 33
5.10 Battery Charger ................................................................................................................... 34
5.11 Hibernation Mode and Wakeup .......................................................................................... 35
5.12 LED Driver ........................................................................................................................... 37
5.13 ΣΔ-ADC Converter .............................................................................................................. 38
5.13.1 How to Measure Input Voltage Higher Than 1.2 V .............................................. 38
5.14 RFIO Port ............................................................................................................................ 40
5.14.1 Antennas and General Considerations................................................................ 41
5.15 PCB Layout ......................................................................................................................... 41
5.15.1 PCB Footprint ...................................................................................................... 41
5.15.2 Microvias or PTH Vias ......................................................................................... 41
5.15.3 Generic PCB Layout Guidelines .......................................................................... 42
5.15.4 PCB Layout for VFBGA100 Package .................................................................. 43
5.15.5 PCB Layout for VFBGA86 Package .................................................................... 47
Revision 1.0
2 of 55
Application Note
CFR0014
22-Feb-2019
© 2019 Dialog Semiconductor
AN-B-066
DA1469x Application Hardware Design Guidelines
5.16 Package Outline Drawing for VFBGA100 and VFBGA86................................................... 50
Appendix A : Hardware Files Deliverables ..................................................................................... 52
Revision History ................................................................................................................................ 54
Figures
Figure 1: DA1469x Packages Comparison ........................................................................................... 7
Figure 2: Block Diagram Of DA1469x Minimal Design ......................................................................... 9
Figure 3: Minimal Design for VFBGA100 Package ............................................................................. 10
Figure 4: Minimal Design for VFBGA86 Package ............................................................................... 11
Figure 5: DA1469x Power Management Unit Block Diagram ............................................................. 12
Figure 6: Power Section of DA1469x SoC .......................................................................................... 13
Figure 7: 4.7 µF/6.3 V Capacitance Change for 0402 Package (Purple) And 0603 Package (Blue) . 15
Figure 8: Effective Capacitance @ V = 1.8 V: ~ 14 µF (fine > 10 µF)................................................. 15
Figure 9: Low VBAT Voltage Power Connection................................................................................. 17
Figure 10: PAD I/O Configuration and the Signals Latched (In Red) .................................................. 18
Figure 11: XTAL32M and XTAL32K Oscillator Circuits....................................................................... 20
Figure 12: XTAL32 Frequency Trimming ............................................................................................ 22
Figure 13: Physical Connection of XTAL32M...................................................................................... 22
Figure 14: Clock Output, Pxy_MODE_REG - PUPD and PID Selection ............................................ 24
Figure 15: Clock Output, GPIO_CLK_SEL - FUNC_CLK_SEL, Clock Selection ............................... 25
Figure 16: Clock Output, System Clocks Output on Fixed Pins .......................................................... 26
Figure 17: QSPI Flash Memory Used in DA1469x DK PRO ............................................................... 28
Figure 18: QSPI RAM Used in DA1469x DK PRO .............................................................................. 28
Figure 19: Recommended Topology for USB Functionality ................................................................ 29
Figure 20: ESD Protection Components on DA1469x DK PRO ......................................................... 30
Figure 21: PCB Layout of ESD Protection Components on DA1469x DK PRO ................................. 30
Figure 22: Relation between Damping and the Step Response of a Series LC Resonator ............... 31
Figure 23: USB Circuit Used for Testing ............................................................................................. 31
Figure 24: Step Responses for 60 cm Cable (Left) and 150 cm Cable (non USB-Cable) (Right). A
Damping Network of 0.39 Ω Resistor and 10 μF Capacitor on VBUS is Used ................................... 31
Figure 25: Step Response for 300 cm Cable (non USB-Cable) and the Damping Network of 0.39 Ω
Resistor and 10 μF Capacitor on VBUS is Used................................................................................. 32
Figure 26: Step Response of VBUS with 0.39 Ω and 10 µF for a 150 cm USB Cable ....................... 32
Figure 27: OVP Applied on DA1469x DK PRO ................................................................................... 33
Figure 28: Vin = 5 V (Left) and Vin = 20 V (Right). Ringing Caused by Long Power Cable ............... 33
Figure 29: Reverse Polarity Protection Circuit Provided from Q3 P-Ch MOSFET.............................. 34
Figure 30: NTC Connections for Battery Temperature Monitoring and Suggested Values ................ 34
Figure 31: Wakeup from Hibernation by USB Cable Being Plugged in, Using GPIO Trigger ............ 36
Figure 32: Set GPIO as Input .............................................................................................................. 36
Figure 33: Set GPIO as Input Pull-down ............................................................................................. 37
Figure 34: DA1469x GPIO Input Levels .............................................................................................. 37
Figure 35: LED Driver Block Diagram ................................................................................................. 38
Figure 36: Accurate NTC Temperature Measurement Using SD-ADC ............................................... 39
Figure 37: RF Matching Circuit must be Placed as Close as Possible to the Antenna ...................... 40
Figure 38: RFIO Circuit........................................................................................................................ 40
Figure 39: Bottom View of Packages VFBGA100 (Left) and VFBGA86 (Right) ................................. 41
Figure 40: Remove Copper on Internal Layer (Right) under XTAL ..................................................... 42
Figure 41: XTAL Grounding ................................................................................................................ 43
Figure 42: PCB Cross Section for VFBGA100 Package ..................................................................... 44
Figure 43: VFBGA100 PCB Layout, L1, Top Side .............................................................................. 44
Figure 44: VFBGA100 PCB Layout, Layer L2 ..................................................................................... 45
Application Note
CFR0014
Revision 1.0
3 of 55
22-Feb-2019
© 2019 Dialog Semiconductor
AN-B-066
DA1469x Application Hardware Design Guidelines
Figure 45: VFBGA100 PCB Layout, Layer L3 ..................................................................................... 45
Figure 46: VFBGA100 PCB Layout, Layer L4 Reference Ground ...................................................... 46
Figure 47: VFBGA100 Ground Connectivity Top (Left) and Pins Location on Chip (Right) ............... 47
Figure 48: PCB Cross Section for VFBGA86 Package ....................................................................... 47
Figure 49: VFBGA86 PCB Layout, L1-Top Layer ............................................................................... 48
Figure 50: VFBGA86 PCB Layout, L2 Layer ....................................................................................... 48
Figure 51: VFBGA86 PCB Layout, L3 Layer, Reference Ground ....................................................... 49
Figure 52: VFBGA86 Ground Connectivity Top (Left) and Pins Location on Chip (Right) ................. 49
Figure 53: POD for VFBGA100 ........................................................................................................... 50
Figure 54: POD for VFBGA86 ............................................................................................................. 51
Figure 55: PRO-DB D2522-db-vfbga100_331_06-x (left) and D2522-db-vfbga86_331-19-x (right) .. 52
Figure 56: DA1469x DK Pro Motherboard: 2522-mb-pro_331-07-x ................................................... 53
Figure 57: DA14695 USB Kit: 2522_devkt-b-usb_331-22-x ............................................................... 53
Tables
Table 1: DA1469x Product Family Differentiation ................................................................................. 6
Table 2: DA1469x Family Chip Options ................................................................................................ 6
Table 3: CHIP_REVISION_REG (0x50040214) ................................................................................... 8
Table 4: CHIP_TEST1_REG (0x500402F8) ......................................................................................... 8
Table 5: Chip Revision Numbering ........................................................................................................ 8
Table 6: Suggested Decoupling Capacitors for the Power Section .................................................... 14
Table 7: SIMO DCDC inductor example and characteristics .............................................................. 15
Table 8: DA1469x Voltage Rails ......................................................................................................... 16
Table 9: DA1469x Pins with RDS Functionality .................................................................................. 18
Table 10: Interfering GPIOs on DA14697 and DA14699 (VFBGA100) .............................................. 19
Table 11: Interfering GPIOs on DA14691 and DA14695 (VFBGA86) ................................................ 20
Table 12: XTAL32M Recommended Operating Conditions ................................................................ 21
Table 13: 32 MHz Crystal Examples and Characteristics ................................................................... 22
Table 14: XTAL32K Recommended Operating Conditions................................................................. 23
Table 15: 32.768 kHz Crystal Example and Characteristics ............................................................... 23
Table 16: System Clocks Mapping to Fixed GPIOs ............................................................................ 25
Table 17: UART Pins ........................................................................................................................... 27
Table 18: JTAG Pins for M33 Core ..................................................................................................... 27
Table 19: JTAG pins for CMAC ........................................................................................................... 27
Table 20: Supported QSPI Flash ........................................................................................................ 28
Application Note
CFR0014
Revision 1.0
4 of 55
22-Feb-2019
© 2019 Dialog Semiconductor
AN-B-066
DA1469x Application Hardware Design Guidelines
1
Terms and Definitions
Bluetooth Low Energy
Chip Select
DC Resistance
Development Kit
General Purpose Input Output
Japan Electronics and Information Technology Industries
Low Drop Out
Medium Access Controller
One Time Programmable
Printed Circuit Board
Power Domain Controller
Power Management Unit
Plated Through Hole
Pulse Width Modulation
Quad-Flat No-leads
Software Development Kit
Single Inductor Multiple Outputs (DCDC converter type)
Serial Peripheral Interface
Static Random-Access Memory
Serial Wire Debug
Universal Asynchronous Receiver/Transceiver
Universal Serial Bus
BLE
CS
DCR
DK
GPIO
JEITA
LDO
MAC
OTP
PCB
PDC
PMU
PTH
PWM
QFN
SDK
SIMO
SPI
SRAM
SWD
UART
USB
2
[1]
[2]
[3]
[4]
References
DA1469x, Datasheet, Dialog Semiconductor.
AN-B-056, DA14680/681 Recovery from System Level ESD Events, Application Note, Dialog
Semiconductor.
AN-B-027, Designing Printed Antennas for Bluetooth Low Energy, Application Note, Dialog
Semiconductor.
UM-B-093, DA1469x PRO Development Kit, User Manual, Dialog Semiconductor.
Application Note
CFR0014
Revision 1.0
5 of 55
22-Feb-2019
© 2019 Dialog Semiconductor
Microcontroller MCU
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