514CCCXXXXXXBAGR datasheet, PDF - EEWORLD Datasheet

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514CCCXXXXXXBAGR: DescriptionClock Generator, 125MHz, CMOS, PDSO6, 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6; CategoryThe embedded processor and controller Microcontrollers and processors; File Size268KB，32 Pages; ManufacturerSilicon Laboratories Inc

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514CCCXXXXXXBAGR Overview

Clock Generator, 125MHz, CMOS, PDSO6, 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6

514CCCXXXXXXBAGR Parametric

Parameter Name	Attribute value
Maker	Silicon Laboratories Inc
Parts packaging code	SOIC
package instruction	LSON,
Contacts	6
Reach Compliance Code	unknown
ECCN code	EAR99
JESD-30 code	R-PDSO-N6
length	5 mm
Number of terminals	6
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	125 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LSON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE
Certification status	Not Qualified
Maximum seat height	1.28 mm
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.2 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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Si514

A

N Y

-F

REQUENCY

I

2

C P

R OG R A MM A B L E

X O ( 1 0 0 k H

Z

Features















TO

250 M H

Z

)

Programmable to any frequency



from 100 kHz to 250 MHz

0.026 ppb frequency tuning



resolution



Glitch suppression on OE, power

on and frequency transitions



1 ps phase jitter (rms, max)

2- to 4-week lead times



Total stability includes 10-year

aging



Comprehensive production test

coverage includes crystal ESR and

DLD

On-chip LDO for power supply

noise filtering

3.3, 2.5, or 1.8 V operation

Differential (LVPECL, LVDS,

HCSL) or CMOS output options

Optional integrated 1:2 CMOS

fanout buffer

Industry standard 5 x 7 and

3.2 x 5 mm packages

–40 to 85

o

C operation

Si5602

Ordering Information:

See page 25.

Pin Assignments:

See page 24.

Applications

All-digital PLLs



DAC+ VCXO replacement



SONET/SDH/OTN



3G-SDI/HD-SDI/SDI



Datacom



Industrial automation



FPGA/ASIC clock generation



FPGA synchronization



SDA

SCL

GND

1

2

3

6

5

4

V

DD

CLK–

CLK+

Description

The Si514 user-programmable I

2

C XO utilizes Silicon Laboratories' advanced PLL

technology to provide any frequency from 100 kHz to 250 MHz with programming

resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and

Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this

range using simple I

2

C commands. Ultra-fine tuning resolution replaces DACs and

VCXOs with an all-digital PLL solution that improves performance where

synchronization is necessary or in free-running reference clock applications. This

solution provides superior supply noise rejection, simplifying low jitter clock

generation in noisy environments. Crystal ESR and DLD are individually

production-tested to guarantee performance and enhance reliability.

The Si514 is factory-configurable for a wide variety of user specifications, including

startup frequency, I

2

C address, supply voltage, output format, and stability. Specific

configurations are factory-programmed at time of shipment, eliminating long lead

times and non-recurring engineering charges associated with custom frequency

oscillators.

Functional Block Diagram

Preliminary Rev. 0.9 3/11

Copyright © 2011 by Silicon Laboratories

Si514

Si514

T

ABLE

Section

OF

C

ONTENTS

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.2. Programming a Small Frequency Change (sub ±1000 ppm) . . . . . . . . . . . . . . . . . . 10

2.3. Programming a Large Frequency Change (> ±1000 ppm) . . . . . . . . . . . . . . . . . . . . 11

3. All-Digital PLL Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4. User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.2. Register Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1. Dual CMOS (1:2 Fanout Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7. Si514 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Preliminary Rev. 0.9

3

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