Features
•
8-bit Microcontroller Compatible with MCS
®
51 Products
•
Enhanced 8051 Architecture
– Single-clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 256 x 8 Internal RAM
– 512 x 8 Internal Extra RAM
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 4K/8K Bytes of In-System Programmable (ISP) Flash Program Memory
– 512/1024 Bytes of Flash Data Memory
– Endurance: Minimum 100,000 Write/Erase Cycles (for Both
Program/Data Memories)
– Serial Interface for Program Downloading
– 64-byte Fast Page Programming Mode
– 128-byte User Signature Array
– 2-level Program Memory Lock for Software Security
– In-Application Programming of Program Memory
Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs
– 4-channel 16-bit Compare/Capture/PWM Array
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Programmable Watchdog Timer with Software Reset
– Dual Analog Comparators with Selectable Interrupts and Debouncing
– 8 General-purpose Interrupt Pins
Special Microcontroller Features
– 2-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Active-low External Reset Pin
– Internal RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
I/O and Packages
– Up to 30 Programmable I/O Lines
– 28-lead PDIP or 32-lead TQFP/PLCC/MLF
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style)
• Input-only (Tristate)
• Push-pull CMOS Output
• Open-drain
Operating Conditions
– 2.4V to 5.5V V
CC
Voltage Range
– -40°C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4–5.5V
– 0 to 25 MHz @ 4.0–5.5V
•
8-bit
Microcontroller
with 4K/8K
Bytes In-System
Programmable
Flash
AT89LP428
AT89LP828
•
•
•
•
3654A–MICRO–8/09
1. Pin Configurations
1.1
28P3 – 28-lead PDIP
1.3
32J – 32-lead PLCC
P3.1/TXD
P3.0/RXD
P2.4/AIN0
P2.5/AIN1
P2.6/AIN2
P2.7/AIN3
P1.7/SCK
AIN1/P2.5
AIN0/P2.4
RXD/P3.0
TXD/P3.1
XTAL2/P4.1
XTAL1/P4.0
GND
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
RST/P3.6
CCD/P2.3
CCC/P2.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P2.6/AIN2
P2.7/AIN3
P1.7/SCK
P1.6/MISO
P1.5/MOSI
P1.4/SS
P1.3
VCC
P1.2
P1.1/T2EX
P1.0/T2
P3.7
P2.0/CCA
P2.1/CCB
1.2
32A – 32-lead TQFP (Top View)
P3.1/TXD
P3.0/RXD
P2.4/AIN0
P2.5/AIN1
P2.6/AIN2
P2.7/AIN3
P1.7/SCK
P1.6/MISO
1.4
32M1-A – 32-pad MLF (Top View)
P3.1/TXD
P3.0/RXD
P2.4/AIN0
P2.5/AIN1
P2.6/AIN2
P2.7/AIN3
P1.7/SCK
P1.6/MISO
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
25
RST/P3.6
CCD/P2.3
CCC/P2.2
CCB/P2.1
CCA/P2.0
P3.7
T2/P1.0
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
14
15
16
17
18
19
20
XTAL2/P4.1
XTAL1/P4.0
P4.5
GND
P4.4
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
P1.6/MISO
P1.5/MOSI
P1.4/SS
P1.3
P4.2
VCC
P4.3
P1.2
P1.1/T2EX
XTAL2/P4.1
XTAL1/P4.0
P4.5
GND
P4.4
INT0/P3.2
INT1/P3.3
T0/P3.4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
P1.5/MOSI
P1.4/SS
P1.3
P4.2
VCC
P4.3
P1.2
P1.1/T2EX
XTAL2/P4.1
XTAL1/P4.0
P4.5
GND
P4.4
INT0/P4.3
INT1/P4.4
T0/P3.4
1
2
3
4
5
6
7
8
P1.5/MOSI
P1.4/SS
P1.3
P4.2
VDD
P4.3
P1.2
P1.1/T2EX
2
AT89LP428/828
3654A–MICRO–8/09
T1/P3.5
RST/P3.6
CCD/P2.3
CCC/P2.2
CCB/P2.1
CCA/P2.0
P3.7T2/
P1.0
T1/P3.5
RST/P3.6
CCD/P2.3
CCC/P2.2
CCB/P2.1
CCA/P2.0
P3.7T2/
P1.0
NOTE:
Bottom pad
should be
soldered to ground
AT89LP428/828
1.5
Pin Description
AT89LP428/828 Pin Description
Table 1-1.
Pin Number
TQFP
/MLF
PLCC
PDIP
Symbol
Type
I/O
O
1
5
5
P4.1
O
I/O
Description
P4.1: User-configurable I/O Port 4
bit
1.
XTAL2: Output from inverting oscillator
amplifier.
It may
be used as a
port pin if the
internal RC oscillator is
selected as
the clock
source.
CLKOUT: When the internal RC oscillator is
selected as
the clock
source,
may
be
used
to output the internal clock divided
by
2.
DDA:
Serial
Data input/output for On-chip Debug Interface when OCD is enabled
and
the external clock is
selected as
the clock
source.
P4.0: User-configurable I/O Port 4
bit
0.
XTAL1: Input to the inverting oscillator
amplifier and
internal clock generation circuits.
It may
be used as a
port pin if the internal RC oscillator is
selected as
the clock
source.
DDA:
Serial
Data input/output for On-chip Debug Interface when OCD is enabled
and
the internal RC oscillator is
selected as
the clock
source.
P4.5: User-configurable I/O Port 4
bit
5.
Ground
P4.4: User-configurable I/O Port 4
bit
4.
P3.2: User-configurable I/O Port 3
bit
2.
INT0: External Interrupt 0 Input or Timer 0 Gate Input.
P3.3: User-configurable I/O Port 3
bit
3.
INT1: External Interrupt 1 Input or Timer 1 Gate Input
P3.4: User-configurable I/O Port 3
bit
4.
T1: Timer/Counter 0 External input or PWM output.
P3.5: User-configurable I/O Port 3
bit
5.
T1: Timer/Counter 1 External input or PWM output.
P3.6: User-configurable I/O Port 3
bit
6 (if Reset Fuse is disabled).
RST: External Active-low Reset input (if Reset Fuse is enabled,
see
“External Reset”
on page 26).
DCL:
Serial
Clock input for On-chip Debug Interface when OCD is enabled.
P2.3: User-configurable I/O Port 2
bit
3.
CCD: Timer 2 Channel D Compare Output or Capture Input.
P2.2: User-configurable I/O Port 2
bit
2.
CCC: Timer 2 Channel C Compare Output or Capture Input.
P2.1: User-configurable I/O Port 2
bit
1.
CCB: Timer 2 Channel B Compare Output or Capture Input.
P2.0: User-configurable I/O Port 2
bit
0.
CCA: Timer 2 Channel A Compare Output or Capture Input.
P3.7: User-configurable I/O Port 3
bit
7.
DDA:
Serial
Data input/output for On-chip Debug Interface when OCD is enabled
and
the Crystal oscillator is
selected as
the clock
source.
P1.0: User-configurable I/O Port 1
bit
0.
T2: Timer 2 External Input or Clock Output.
GPI0: General-purpose Interrupt input 0.
I/O
I
2
6
6
P4.0
I/O
3
4
5
6
7
8
9
7
8
9
10
11
12
13
N/A
7
N/A
8
9
10
11
P4.5
GND
P4.4
P3.2
P3.3
P3.4
P3.5
I/O
I
I/O
I/O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I
10
14
12
P3.6
11
12
13
14
15
16
17
18
13
14
15
16
P2.3
P2.1
P2.1
P2.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
15
19
17
P3.7
16
20
18
P1.0
3
3654A–MICRO–8/09
Table 1-1.
AT89LP428/828 Pin Description (Continued)
Pin Number
TQFP
/MLF
17
PLCC
21
PDIP
19
Symbol
P1.1
Type
I/O
I
I
I/O
I
I/O
I
I/O
I/O
I
I/O
I
I
I/O
I/O
I
I/O
I/O
I
I/O
I/O
I
27
28
29
30
31
32
31
32
1
2
3
4
27
28
1
2
3
4
P2.6
P2.7
P2.5
P2.4
P3.0
P3.1
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
Description
P1.1: User-configurable I/O Port 1
bit
1.
T2EX: Timer 2 External Capture/Reload Input.
GPI1: General-purpose Interrupt input 1.
P1.2: User-configurable I/O Port 1
bit
2.
GPI2: General-purpose Interrupt input 2.
P4.3: User-configurable I/O Port 4
bit
3.
Supply
Voltage.
P4.2: User-configurable I/O Port 4
bit
2.
P1.3: User-configurable I/O Port 1
bit
3.
GPI3: General-purpose Interrupt input 3.
P1.4: User-configurable I/O Port 1
bit
4.
SS: SPI Slave-select.
GPI6: General-purpose Interrupt input 4.
P1.5: User-configurable I/O Port 1
bit
5.
MOSI:
SPI
master-out/slave-in. When configured
as
master, this pin is
an
output.
When configured
as slave,
this pin is
an
input.
GPI5: General-purpose Interrupt input 5.
P1.6: User-configurable I/O Port 1
bit
6.
MISO:
SPI
master-in/slave-out. When configured
as
master, this pin is
an
input.
When configured
as slave,
this pin is
an
output.
GPI6: General-purpose Interrupt input 6.
P1.7: User-configurable I/O Port 1
bit
7.
SCK: SPI
Clock. When configured
as
master, this pin is
an
output. When
configured
as slave,
this pin is
an
input.
GPI7: General-purpose Interrupt input 7.
P2.6: User-configurable I/O Port 2
bit
6.
AIN2: Analog Input 2.
P2.7: User-configurable I/O Port 2
bit
7.
AIN3: Analog Input 3.
P2.5: User-configurable I/O Port 2
bit
5.
AIN1: Analog Input 1.
P2.4: User-configurable I/O Port 2
bit
5.
AIN0: Analog Input 0.
P3.0: User-configurable I/O Port 3
bit
0.
RXD:
Serial
Port Receiver Input.
P3.1: User-configurable I/O Port 3
bit
1.
TXD:
Serial
Port Transmitter Output.
18
19
20
21
22
22
23
24
25
26
20
N/A
21
N/A
22
P1.2
P4.3
VCC
P4.2
P1.3
23
27
23
P1.4
24
28
24
P1.5
25
29
25
P1.6
26
30
26
P1.7
4
AT89LP428/828
3654A–MICRO–8/09
AT89LP428/828
2. Overview
The AT89LP428/828 is
a
low-power, high-performance CMOS 8-bit microcontroller with 4K/8K
bytes
of In-System Programmable Flash program memory
and
512/1024
bytes
of Flash data
memory. The device is manufactured
using
Atmel
®
's
high-density nonvolatile memory technol-
ogy
and
is compatible with the industry-standard MCS51 instruction
set.
The AT89LP428/828 is
built around an
enhanced CPU core that can fetch
a single byte
from memory every clock cycle.
In the classic 8051
architecture,
each fetch requires 6 clock cycles, forcing instructions to exe-
cute in 12, 24 or 48 clock cycles. In the AT89LP428/828 CPU, instructions need only 1 to 4 clock
cycles providing 6 to 12 times more throughput than the
standard
8051.
Seventy
percent of
instructions need only
as
many clock cycles
as
they have
bytes
to execute,
and
most of the
remaining instructions require only one
additional
clock. The enhanced CPU core is capable of
20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS
at
the
same
current
consumption. Conversely,
at
the
same
throughput
as
the classic 8051, the new CPU core runs
at a
much lower
speed and
thereby greatly reducing power consumption
and
EMI.
The AT89LP428/828 provides the following
standard
features: 4K/8K
bytes
of In-System
Programmable Flash program memory, 512/1024
bytes
of Flash data memory, 768
bytes
of
RAM,
up
to 30 I/O lines, three 16-bit timer/counters,
up
to
six
PWM outputs,
a
programmable
watchdog timer, two
analog
comparators,
a
full-duplex
serial
port,
a serial
peripheral interface,
an
internal RC oscillator, on-chip crystal oscillator,
and a
four-level, ten-vector interrupt
system.
A
block
diagram is
shown
in
Figure 2-1 on page 6.
Timer 0
and
Timer 1 in the AT89LP428/828
are
enhanced with two new modes. Mode 0 can
be
configured
as a
variable 9- to 16-bit timer/counter
and
Mode 1 can
be
configured
as a
16-bit
auto-reload
timer/counter. In
addition,
the timer/counters may independently drive
an
8-bit preci-
sion
pulse width modulation output.
Timer 2 on the AT89LP428/828
s
erve
s as a
16-
b
it time
bas
e for
a
4-ch
a
nnel
Compare/Capture Array with
up
to four multi-phasic, variable precision PWM outputs.
The enhanced UART of the AT89LP428/828 includes Framing Error Detection
and
Automatic
Address Recognition. In
addition,
enhancements to Mode 0
allow
hardware
accelerated
emula-
tion of half-duplex
SPI
or 2-wire interfaces.
The I/O ports of the AT89LP428/828 can
be
independently configured in one of four operating
modes. In quasi-bidirectional mode, the ports operate
as
in the classic 8051. In input-only mode,
the ports
are
tristated. Push-pull output mode provides full CMOS drivers
and
open-drain mode
provides just
a
pull-down. In
addition, all
8 pins of Port 1 can
be
configured to generate
an
inter-
rupt
using
the General-purpose Interrupt (GPI) interface.
5
3654A–MICRO–8/09
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