Autorecovery if the overcurrent is less than 104% and last only for <500 ms.
Standby protection is auto-recovery
Minimum current for transient load response testing only. Unit is designed to operate and be wtihin regulation range at zero load.
Revere airflow model derates to 231.5 A
DS3000PE Data Sheet
Control and Status Signals
Input Signals
PSON
Active LOW signal which enables/disables the main output. Pulling this signal LOW will turn-on the main output.
Recommended pull-up resistor to 12 VSB is 8.2 k with a 3.0 k pull-down to ground. A 100 pF decoupling capacitor is also recommended.
MIN
V
IL
V
IH
I
SOURCE
I
SINK
PSKIL
First break/last mate active LOW signal which enables/disables the main output. This signal will have to be pulled to ground at the system side with a 220 ohm
resistor. A 100 pF decoupling capacitor is also recommended.
MIN
V
IL
V
IH
I
SOURCE
I
SINK
A0, A1, A2
Addressing pins of the power supply for I
2
C communications. Refer to the addressing tables below.
MIN
Internal pull-ups to 3.3V.
It is recommended for the system to have pull-ups and
decoupling on the address lines for better noise immunity.
V
IL
V
IH
I
SOURCE
I
SINK
Input logic level LOW
Input logic level HIGH
Current that may be sourced by this pin
Current that may be sunk by this pin
4 mA
2.0 V
0.8 V
5.0 V
4 mA
R = 22 k ohm
MAX
C = 47 pF
Input logic level LOW
Input logic level HIGH
Current that may be sourced by this pin
Current that may be sunk by this pin at low state
2.0 V
MAX
0.8 V
5.0 V
2 mA
0.5 mA
Input logic level LOW
Input logic level HIGH
Current that may be sourced by this pin
Current that may be sunk by this pin at low state
2.0 V
MAX
0.8 V
5.0 V
2 mA
0.5 mA
Output Signals
ACOK
Signal used to indicate the presence of AC input to the power supply. A logic level HIGH will indicate that the AC input to the power supply is within the operating
range while a logic level LOW will indicate that AC has been lost.
This is an open collector/drain output. This pin is pulled high by a 1.0 k ohm resistor connected to 3.3 V inside the power supply.
It is recommended that this pin be connected to a 100 pF decoupling capacitor and pulled down by a 100 k ohm resistor.
MIN
V
IL
V
IH
I
SOURCE
I
SINK
Output logic level LOW
Output logic level HIGH
Current that may be sourced by this pin
Current that may be sunk by this pin at low state
2.0 V
MAX
0.6 V
5.0 V
3.3 mA
0.7 mA
DS3000PE Data Sheet
Control and Status Signals
PWR_GOOD / PWOK
Signal used to indicate that main output voltage is within regulation range. The PWR_GOOD signal will be driven HIGH when the output voltage is valid and will be
driven LOW when the output falls below the under-voltage threshold.
This signal also gives an advance warning when there is an impending power loss due to loss of AC input or system shutdown request. More details in the Timing Section.
This is an open collector/drain output. This pin is pulled high by a 1.0 k ohm resistor connected to 3.3 V inside the power supply. It is recommended that this pin be
connected to a 100 pF decoupling capacitor and pulled down by a 10 k ohm resistor.
MIN
V
IL
V
IH
I
SOURCE
I
SINK
PS_PRESENT
Signal used to indicate to the system that a power supply is inserted in the power bay. Recommended pull-up resistor to 12 VSB is 8.2 k with a 3.0 k pull-down to
ground. A 100 pF decoupling capacitor is also recommended.
PS_INTERRUPT
Active low signal used by the power supply to indicate to the system that a change in power supply status has occurred. This event can be triggered by faults
such as OVP, OCP, OTP, and fan fault. This signal can be cleared by a CLEAR_FAULT command. Recommended pull-up resistor to 12 VSB is 8.2 k with a 3.0 k
pull-down to ground. A 100 pF decoupling capacitor is also recommended.
MIN
V
IL
V
IH
I
SOURCE
I
SINK
Output logic level LOW
Output logic level HIGH
Current that may be sourced by this pin
Current that may be sunk by this pin at low state
2.0 V
MAX
0.8 V
5.0 V
4 mA
4 mA
Output logic level LOW
Output logic level HIGH
Current that may be sourced by this pin
Current that may be sunk by this pin at low state
2.0 V
MAX
0.8 V
5.0 V
3.3 mA
0.7 mA
BUS Signals
ISHARE
Bus signal used by the power supply for active current sharing. All power supplies configured in the system for n+n sharing will refer to this bus voltage inorder to
load share.
Voltage Range
I
SHARE
Voltage
The range of this signal for active sharing will be up to 8.0 V, which corresponds to the maximum output current.
MIN
Input logic level LOW
Voltage at 50% load, stand-alone unit
Voltage at 0% load, stand-alone unit
I
SOURCE
SCL, SDA
Clock, data and addressing signals defined as per I
2
C requirements. The maximum system side resistor pull-up and decoupling capacitance
MIN
V
L
V
H
Logic level LOW
Logic level HIGH
2.0 V
MAX
0.8 V
5.0 V
Current that may be sourced by this pin
7.75
3.85
0
MAX
8.25
4.15
0.3
160 mA
Note:
All signal noise levels are below 400 mVpk-pk from 0 - 100 MHz.
I
2
C Addressing Table
FRU ADDRESSING
A2
HIGH
HIGH
HIGH
HIGH
A1
LOW
LOW
HIGH
HIGH
A0
LOW
HIGH
LOW
HIGH
Address
0 x A9
0 x AB
0 x AD
0 x AF*
PMBus Addressing
Address
0 x B8
0 x BA
0 x BC
0 x BE
* Default address when AO and A1 are open
DS3000PE Data Sheet
Electrical Specifications
LED Indicators
AC GOOD LED
Color
No AC input to PSU
AC present, STBY ON, main output OFF
Main output ON
Power supply failure (OVP, OTP, FAN FAULT)
GREEN
Off
On
On
Off
DC GOOD LED
GREEN
Off
Off
On
Off
FAULT LED
AMBER
Off
Off
Off
Blinking
Firmware Reporting And Monitoring
Accuracy Range
Output loading
Input voltage
Input current
Input power
Output voltage
Output current
Temperature
E
IN
Fan speed
±15% from 10% to 20% load
±250 RPM
2.5 A fixed error
±5 degC on the operating range
±5%
±0.55 A fixed error
±10 W at < 100 W input
±2%
±2%
5 to 20%
20 to 50%
±5%
±4%
±5%
50 to 100%
PMBus
Remote ON/OFF
YES
YES
Timing Specifications
Description
T
sb_On
T
sb_vout
T
sb_ACOK
T
ac_on_delay
T
pwok_on
T
acok_delay
T
pwok_hold-up
T
vout_hold-up
T
sb_Hold-up
T
PWR_GOOD_Off
T
PSON_On_Delay
Delay from AC being applied to standby output being within regulation
Delay from standby output to main output voltage being within regulation
Delay from standby output to ACOK assertion
Delay from AC being applied to main output being within regulation
Delay from output voltages within regulation limits to PWOK asserted
Delay from loss of AC to assertion of ACOK
Delay from loss of AC to deassertion of PWOK
Delay from loss of AC to main output falling out of regulation
Delay from loss of AC to standby output being within regulation
Delay from deassertion of PWOK to output falling out of regulation
Delay from PSON assertion to output being within regulation
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