530UC602M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530UC602M000DGR

530UC602M000DGR: DescriptionCMOS/TTL Output Clock Oscillator, 602MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530UC602M000DGR Overview

CMOS/TTL Output Clock Oscillator, 602MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530UC602M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	602 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

WYJ81 type automatic AC regulated power supply circuit

Delay light circuit using music integrated circuit

HT-1391 circuit

Oscillators using FETs and transistors

Bridge pickup type speaker protection circuit (1)

What is the current status of the LED industry?: I knew about the LED industry a long time ago, but I never got a deep understanding of it. Today, I met a buddy while hiking. He boasted to me: 1. There are too many orders to complete, and we have to...; 半导体狂人 LED Zone

How can I save my changes to the system settings after Windows CE restarts?: 1. I developed a program myself and baked it into the Windows CE system. After restarting, it disappeared, including the touch screen settings and the USB conection settings. 2. Which registry key val...; hzwwqq Embedded System

The Surrender of Bandits at Birdcage Mountain: Hu Ge's new work http://www.6rooms.com/nlsdwatch.php?v=2755 is really funny. Hu Ge almost went bankrupt to make this film. Someone on the Internet awarded him the Golden Bun Award, with pictures and t...; 6294316 Talking

Urgent, please provide a driver file for MSP430 LSD-FET430UIF emulator! !: I installed a 5.5 version yesterday, but it doesn't work. The emulator doesn't respond when connected to the PC! The port in the computer device manager shows MSP-FET430UIF-CDC (COM4). I thought the d...; Double.L Microcontroller MCU

Doubts about 2410 awakening: The platform I use is 2410, the system is CE5.0, and I encountered the following problems when doing power management 1. It can sleep. After CPUPOWEROFF in fw.s, the system can be determined to be in ...; spring_hsq Embedded System

【Design Tools】Xilinx FPGA PLL Dynamic Reconfiguration Techniques: This application note first introduces a method to dynamically modify the clock output frequency, phase shift, and duty cycle of the Spartan-6 FPGA phase-locked loop (PLL) through the dynamic reconfig...; GONGHCU FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components