54RHST74NC datasheet, PDF - EEWORLD Datasheet

54RHST74NC: DescriptionD Flip-Flop, HST/T Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, DIE; Categorylogic logic; File Size2MB，84 Pages; ManufacturerDynex; Websitehttp://www.dynexsemi.com/

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54RHST74NC Overview

D Flip-Flop, HST/T Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, DIE

Parameter Name	Attribute value
Parts packaging code	DIE
package instruction	DIE,
Reach Compliance Code	unknow
Other features	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY
series	HST/T
JESD-30 code	X-XUUC-N
Logic integrated circuit type	D FLIP-FLOP
Number of digits	1
Number of functions	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	UNSPECIFIED
encapsulated code	DIE
Package shape	UNSPECIFIED
Package form	UNCASED CHIP
propagation delay (tpd)	25 ns
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal location	UPPER
Trigger type	POSITIVE EDGE
Base Number Matches	1

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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