Delivering Next Generation Technology
Series
FPMR05SR7506*A
2.4-5.5Vdc Input, 6A, 0.7525-3.63Vdc Output
The
Series of non-isolated dc-dc converters
deliver
exceptional
electrical
and
thermal
performance in industry-standard footprints for
Point-of-Load converters. Operating from a
2.4Vdc-5.5Vdc input, these are the converters of
choice for Intermediate Bus Architecture (IBA) and
Distributed Power Architecture applications that
require high efficiency, tight regulation, and high
reliability in elevated temperature environments with
low airflow.
非絶縁型DC/DC½ﾝﾊﾞ½ﾀの
½ﾘ½½½ﾞは業界標準のPOL½ﾝﾊﾞ½ﾀ
と同じ端子配列で極めて優れた電気的特性、及び温度特性を提供しま
す。
入力電圧2.4V-5.5Vで動½しますので、この½ﾝﾊﾞ½ﾀは、高効率、高い出
力電圧精度、高温、及び風量の少ない環境での高信頼性が要求される
IBA、又はDPAでの½用に最適です。
FPMR05SR7506*A
Features
•
RoHS compliant
RoHS準拠
•
Delivers up to 6A (21.78W)
6A (21.78W)まで供給可½
The
FPMR05SR7506*A
converter of the
Series delivers 6A of output current at a tightly
regulated programmable output voltage of 0.7525Vdc
to 3.63Vdc. The thermal performance of the
FPMR05SR7506*A
is best-in-class: No derating is
needed up to 85℃, under natural convection.
½ ﾘ ½ ½½ ﾞ の FPMR05SR7506*A は高 い 電 圧 精 度 で0.7525V ½
3.63Vの可変を実現します。FPMR05SR7506*Aの温度特性は½ﾗ½½最高
ﾚﾍﾞﾙです。自然対流条件で85℃までﾃﾞ½ﾚ½ﾃ½ﾝ½ﾞを必要としません。
•
High efficiency, no heatsink required
高効率-放熱器が不要
•
Negative and Positive ON/OFF logic
ON/OFFﾛ½ﾞ½½はﾈ½ﾞﾃ½ﾌﾞとﾎﾟ½ﾞﾃ½ﾌﾞ
•
Industry-standard SMD footprint
業界標準のSMDﾌ½ﾄﾌﾟﾘﾝﾄ
This leading edge thermal performance results from
electrical, thermal and packaging design that is
optimized for high density circuit card conditions.
Extremely high quality and reliability are achieved
through advanced circuit and thermal design
techniques and FDK’s state of the art in-house
manufacturing processes and systems.
回路設計、放熱設計、及びﾊﾟ½½½½ﾞﾝ½ﾞ設計の結果である最先端の温
度特性は、高密度実装回路用に最適化されています。非常に優れた品
質と信頼性は高度な回路設計、温度設計技術、及びFDKの最先端の
自社½造ﾌﾟﾛ½½½によりもたらされます。
•
Small size and low profile: 0.80” x 0.45” x 0.211”
nominal
小型、½背 (20.3 x 11.4 x 5.35mm)
•
Coplanarity less than 0.004”
平面度は0.1mm以下
•
Tape & reel packaging
梱包はﾃ½ﾋﾟﾝ½ﾞ仕様
•
Programmable output voltage via external resistor
外部接続の抵抗によりﾌﾟﾛ½ﾞﾗﾑ可½な出力電圧
•
No minimum load required
•
Start up into pre-biased output
出力にﾌﾟﾘﾊﾞ½½½½があっても起動可½
最小負荷は不要
Applications
•
Intermediate Bus Architecture
中間ﾊﾞ½½構成½½½ﾃﾑ
•
Remote ON/OFF
ﾘﾓ½ﾄON/OFF機½
•
Auto-reset output over-current protection
過電流保護機½: 自動復帰
•
Auto-reset over-temperature protection
内部加熱保護機½: 自動復帰
•
Telecommunications
ﾃﾚ½ﾑ½½½ﾃﾑ
•
High reliability, MTBF = 1 Million Hours
高信頼性: MTBF = 1 Million Hours
•
Data/Voice processing
ﾃﾞ½ﾀ処理½½½ﾃﾑ
•
Distributed Power Architecture
分散型電源½½½ﾃﾑ
•
UL60950 recognition in U.S. & Canada, and CB
Scheme certification per IEC/EN60950 (Pending)
UL60950、CB Schemeを取得(予定)
•
Computing (Servers, Workstations)
½ﾝﾋﾟ½½ﾀ関係(½½ﾊﾞ½、ﾜ½½½½ﾃ½½½ﾝ)
•
All materials meet UL94, V-0 flammability rating
全ての部品は UL94 V-0に適合
http://www.fdk.com
Page 1 of 26
Ver 2.3 Nov. 05, 2007
Delivering Next Generation Technology
Series
FPMR05SR7506*A
Electrical Specifications
2.4-5.5Vdc Input, 6A, 0.7525-3.63Vdc Output
電気的仕様
All specifications apply over specified input voltage, output load, and temperature range, unless otherwise
noted.
注記が無い場合、全ての仕様は指定された入力電圧、負荷、温度範囲で適用されます。
Conditions: Ta=25degC, Airflow=200LFM (1.0m/s), Vin=5.0Vdc, unless otherwise specified.
PARAMETER
ABSOLUTE MAXIMUM RATINGS
1
Input Voltage
Operating Temperature
Storage Temperature
Output Voltage
FEATURE CHARACTERISTICS
Switching Frequency
Output Voltage Programming Range
Turn-On Delay Time
with Vin (module enabled, then Vin applied)
with Enable (Vin applied, then enabled)
Rise Time (Full resistive load)
ON/OFF Control (Negative Logic)
Module Off
Module On
ON/OFF Control (Positive Logic)
Module Off
Module On
Continuous
NOTES
MIN
TYP
MAX
UNITS
-0.3
-40
-55
0.7525
6.0
85
125
3.63
Vdc
°C
°C
Vdc
Ambient temperature
300
By external resistor. See trim table-1
Full resistive load
From Vin=Vin(min) to 0.1*Vout(nom)
From enable to 0.1*Vout(nom)
From 0.1*Vout(nom) to 0.9*Vout(nom)
See Page26. Part Numbering Scheme
2.4
-5.0
See Page26. Part Numbering Scheme
-5.0
Vin-0.8
Vin-1.6
Vin
Vdc
Vdc
Vin
0.8
Vdc
Vdc
5
5
5
ms
ms
ms
0.7525
3.63
Vdc
1
Absolute Maximum Ratings
絶対最大定格
Stresses in excess of the absolute maximum ratings may lead to degradation in performance and reliability of
the converter and may result in permanent damage.
絶対最大定格を超えた½½ﾄﾚ½½は、性½の½下、長期信頼性の½下、及びﾓ½ﾞ½½ﾙの破損を引き起こすことがあります。
http://www.fdk.com
Page 2 of 26
Ver 2.3 Nov. 05, 2007
Delivering Next Generation Technology
Series
FPMR05SR7506*A
2.4-5.5Vdc Input, 6A, 0.7525-3.63Vdc Output
Electrical Specifications (Continued)
電気的仕様 (続き)
Conditions: Ta=25degC, Airflow=200LFM (1.0m/s), Vin=5.0Vdc, unless otherwise specified.
PARAMETER
INPUT CHARACTERISTICS
Operating Input Voltage Range
Vout
≦ 1.8V
NOTES
MIN
TYP
MAX
UNITS
2.4
3.3
4.5
5.0
5.0
5.0
5.5
5.5
5.5
Vdc
Vdc
Vdc
1.8V < Vout
≦
2.5V
Vout
≧
3.3V (ALL)
Input Under Voltage Lockout
Turn-on Threshold
Turn-off Threshold
Maximum Input Current
6Aout at Vin min
Vout=3.3V
Vout=2.5V
Vout=2.0V
Vout=1.8V
Vout=1.5V
Vout=1.2V
Vout=1.0V
Vout=0.7525V
Input Stand-by Current (module disabled)
Input No Load Current
Vout=3.3V
Vout=2.5V
Vout=2.0V
Vout=1.8V
Vout=1.5V
Vout=1.2V
Vout=1.0V
Vout=0.7525V
Input Reflected-Ripple Current
See Fig. G for setup (BW=20MHz)
2.2
1.95
2.1
2.4
Vdc
Vdc
4.73
4.94
4.02
5.02
4.25
3.49
2.99
2.36
2
53
60
58
56
46
42
38
32
35
Adc
Adc
Adc
Adc
Adc
Adc
Adc
Adc
mA
mA
mA
mA
mA
mA
mA
mA
mA
mAp-p
http://www.fdk.com
Page 3 of 26
Ver 2.3 Nov. 05, 2007
Delivering Next Generation Technology
Series
FPMR05SR7506*A
2.4-5.5Vdc Input, 6A, 0.7525-3.63Vdc Output
Electrical Specifications (Continued)
PARAMETER
OUTPUT CHARACTERISTICS
Output Voltage Set Point (no load)
Output Regulation
Over Line
Over Load
Output Voltage Range
(Over all operating input voltage, resistive load
and temperature conditions until end of life)
Output Ripple and Noise BW=20MHz
Peak to Peak
External Load Capacitance
Min ESR > 1mΩ
Min ESR > 10mΩ
Output Current Range
Output Current Limit Inception (Iout)
Output Short-Circuit Current
DYNAMIC RESPONSE
Iout step from 3A to 6A with di/dt= 5A/µS
Setting time (Vout < 10% peak deviation)
Iout step from 6A to 3A with di/dt= -5A/µS
Setting time (Vout < 10% peak deviation)
EFFICIENCY
電気的仕様 (続き)
NOTES
MIN
TYP
MAX
UNITS
Conditions: Ta=25degC, Airflow=200LFM (1.0m/s), Vin=5.0Vdc, unless otherwise specified.
-1.5
Vout
+1.5
%Vout
Full resistive load
From no load to full load
-2.5
Over line, load and temperature (Fig. F)
Vout=3.3Vdc
Plus full load (resistive)
+/- 0.3
+/- 0.5
+2.5
%Vout
%Vout
%Vout
40
70
mVp-p
1000
2000
0
Vout=3.3Vdc
Short=10mΩ, Vout=3.3Vdc set
9.6
3.5
6
µF
µF
A
A
Arms
Co=47µF x 2 ceramic + 1µF ceramic
100
40
mV
µS
mV
µS
Co=47µF x 2 ceramic + 1µF ceramic
100
40
Full load (6A)
Vout=3.3Vdc
Vout=2.5Vdc
Vout=2.0Vdc
Vout=1.8Vdc
Vout=1.5Vdc
Vout=1.2Vdc
Vout=1.0Vdc
Vout=0.7525Vdc
93.5
91.5
90.0
89.0
87.5
85.0
82.5
78.0
%
%
%
%
%
%
%
%
http://www.fdk.com
Page 4 of 26
Ver 2.3 Nov. 05, 2007
Delivering Next Generation Technology
Series
FPMR05SR7506*A
Operation
Input and Output Impedance
The
FPMR05SR7506*A
converter should be
connected to a DC power source using a low
impedance input line. In order to counteract the
possible effect of input line inductance on the stability
of the converter, the use of decoupling capacitors
placed in close proximity to the converter input pins is
recommended. This will ensure stability of the
converter and reduce input ripple voltage. Although
low ESR Tantalum or other capacitors should
typically be adequate, very low ESR capacitors
(ceramic, over 200µF) are recommended to minimize
input ripple voltage. The converter itself has on-board
internal input capacitance of 5x2.2µF with very low
ESR (ceramic).
FPMR05SR7506*Aと入力電源間は½½ﾝﾋﾟ½ﾀﾞﾝ½½で接続してください。½
ﾝﾊﾞ½ﾀの安定性に½響のある入力½ﾝﾀﾞ½ﾀﾝ½½を抑えるため、½ﾝﾊﾞ½ﾀの
入力ﾋﾟﾝの近傍にﾃﾞ½½ﾌﾟﾘﾝ½ﾞ½ﾝﾃﾞﾝ½を付加することをお勧めします。こ
れにより½ﾝﾊﾞ½ﾀの安定動½を確実にし、入力ﾘ½ﾌﾟﾙ電圧を抑制します。
½ESRﾀﾝﾀﾙ、又はその他の½ﾝﾃﾞﾝ½も一般的には問題ありませんが、
入力ﾘ½ﾌﾟﾙを最小にするためには、非常に½ESR½ﾝﾃﾞﾝ½(½ﾗﾐ½½で200
μF以上)を推奨します。½ﾝﾊﾞ½ﾀ自身は入力回路に極½ESRの5x2.2μF
½ﾗﾐ½½入力½ﾝﾃﾞﾝ½を搭載しています。
2.4-5.5Vdc Input, 6A, 0.7525-3.63Vdc Output
ON/OFF (Pin 5)
The ON/OFF pin (pin 5) can be used to turn the
converter on or off remotely using a signal that is
referenced to GND (pin 2), as shown in Fig. A.
Two remote control options are available,
corresponding to negative and positive logic. In the
negative logic option, to turn the converter on Pin 5
should be at logic low or left open, and to turn the
converter off Pin 5 should be at logic high or
connected to Vin. In the positive logic option, to turn
the converter on Pin 5 should be at logic high,
connected to Vin or left open, and to turn the
converter off Pin 5 should be at logic low.
ON/OFF端子(5番ﾋﾟﾝ)は図Aのように、½ﾞﾗﾝﾄﾞ(2番ﾋﾟﾝ)を基準としたﾘﾓ½ﾄ
信号により½ﾝﾊﾞ½ﾀをON/OFFするのに½われます。 ﾈ½ﾞﾃ½ﾌﾞとﾎﾟ½ﾞﾃ½ﾌﾞ
ﾛ½ﾞ½½に対応するため、2種類のﾘﾓ½ﾄ½ﾝﾄﾛ½ﾙを選択可½です。
ﾈ½ﾞﾃ½ﾌﾞ½ﾌﾟ½½ﾝの場合、½ﾝﾊﾞ½ﾀをONするには5番ﾋﾟﾝをLowﾚﾍﾞﾙ、又は
未接続とし、½ﾝﾊﾞ½ﾀをOFFするには5番ﾋﾟﾝをHighﾚﾍﾞﾙ、又はVinと接続
とします。ﾎﾟ½ﾞﾃ½ﾌﾞ½ﾌﾟ½½ﾝの場合、½ﾝﾊﾞ½ﾀをONするには5番ﾋﾟﾝをHighﾚ
ﾍﾞﾙ、Vinに接続、又は未接続とし、½ﾝﾊﾞ½ﾀをOFFするには5番ﾋﾟﾝをLow
ﾚﾍﾞﾙにします。
The
FPMR05SR7506*A
is capable of stable
operation with no external capacitance on the output.
To minimize output ripple voltage, the use of very low
ESR ceramic capacitors is recommended. These
capacitors should be placed in close proximity to the
load to improve transient performance and to
decrease output voltage ripple.
FPMR05SR7506*Aは出力に外付け½ﾝﾃﾞﾝ½が無い状態でも安定して動
½します。出力ﾘ½ﾌﾟﾙを最小にするため、極½ESRの½ﾗﾐ½½½ﾝﾃﾞﾝ½の接
続を推奨します。過渡時の特性向上と出力ﾘ½ﾌﾟﾙ½減のために負荷の
近傍に極½ESR½ﾗﾐ½½½ﾝﾃﾞﾝ½を実装することをお勧めします。
For a positive logic option, the ON/OFF pin (pin5) is
internally pulled-up to Vin. An open collector (open
-drain) transistor can be used to drive Pin 5.
The device driving Pin 5 must be capable of:
(a) Sinking up to 0.4mA at low logic level
ﾎﾟ½ﾞﾃ½ﾌﾞ½ﾌﾟ½½ﾝの場合、ON/OFFﾋﾟﾝはﾓ½ﾞ½½ﾙ内部でVinにﾌﾟﾙ½½ﾌﾟさ
れています。½½ﾌﾟﾝ½ﾚ½ﾀ（½½ﾌﾟﾝﾄﾞﾚ½ﾝ）のﾄﾗﾝ½ﾞ½½ﾀがON/OFFﾋﾟﾝの操
½に½用可½です。
ON/OFFﾋﾟﾝを操½するﾃﾞﾊﾞ½½½には下記½力が必要です。
(a) Lowﾚﾍﾞﾙで0.4mA程度の½ﾝ½½力
Note that the converter does not have a SENSE pin
to counteract voltage drops between the output pins
and the load. The impedance of the line from the
converter output to the load should thus be kept as
low as possible to maintain good load regulation.
この½ﾝﾊﾞ½ﾀは出力端子と負荷間の電圧ﾄﾞﾛ½ﾌﾟを補正する½ﾝ½½端子を設
けていません。精度の高い負荷特性を保持するために、½ﾝﾊﾞ½ﾀの出力
から負荷までのﾗ½ﾝ½ﾝﾋﾟ½ﾀﾞﾝ½½は可½な限り½くしてください。
For a negative logic option, the ON/OFF pin (pin5) is
internally pulled-down.A TTL or CMOS logic gate,
open collector(open-drain) transistor can be used to
drive Pin 5. When using an open collector(open
-drain) transistor, a pull-up resistor, R*=5kΩ, should
be connected to Vin (See Fig. A).
The device driving Pin 5 must be capable of:
(b) Sinking up to 1.2mA at low logic level (≦0.8V)
(c) Sourcing up to 0.25mA at high logic level (2.3-5V)
ﾈ½ﾞﾃ½ﾌﾞ½ﾌﾟ½½ﾝの場合、ON/OFFﾋﾟﾝはﾓ½ﾞ½½ﾙ内部でﾌﾟﾙﾀﾞ½ﾝされてい
ます。TTL、 CMOSﾛ½ﾞ½½、又は½½ﾌﾟﾝ½ﾚ½ﾀのﾄﾗﾝ½ﾞ½½ﾀもON/OFFﾋﾟﾝの
操½に½用可½です。½½ﾌﾟﾝ½ﾚ½ﾀのﾄﾗﾝ½ﾞ½½ﾀを½用する時は5kΩのﾌﾟ
ﾙ½½ﾌﾟ抵抗をVinに接続してください。(図A参照)
ON/OFFﾋﾟﾝを操½するﾃﾞﾊﾞ½½½には下記½力が必要です。
(b) 0.8V以下のLowﾚﾍﾞﾙで1.2mAまでの½ﾝ½½力
(c) 2.3V-5VのHighﾛ½ﾞ½½ﾚﾍﾞﾙで0.25mAまでの供給½力
Vin
Vout
R*
Vin
ON/OFF
Rload
GND
CONTROL
INPUT
TRIM
R* is for negative logic option only
Fig. A: Circuit configuration for remote ON/OFF
http://www.fdk.com
Page 5 of 26
Ver 2.3 Nov. 05, 2007
京公网安备 11010802033920号
EEWORLD
