The CY7C1041BNV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041BNV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
INPUT BUFFER
Pin Configuration
SOJ
TSOP II
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
256K x 16
ARRAY
1024 x 4096
I/O
0
– I/O
7
I/O
8
– I/O
15
COLUMN
DECODER
BHE
WE
CE
OE
BLE
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
14
A
13
A
12
A
11
A
10
ROW DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 001-06434 Rev. **
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 1, 2006
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CY7C1041BNV33
Selection Guide
-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Comm’l
Ind’l
Com’l/Ind’l
Com’l
L
12
190
-
8
0.5
-15
15
170
190
8
0.5
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
–40°C to +85°C
V
CC
3.3V ± 0.3V
Electrical Characteristics
Over the Operating Range
-12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Leakage Current
Output Leakage Current
V
CC
Operating
Supply Current
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Comm’l
Ind’l
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–1
–1
Min.
2.4
0.4
V
CC
+0.5
0.8
+1
+1
190
-
40
8
0.5
2.2
–0.5
–1
–1
Max.
Min.
2.4
0.4
V
CC
+0.5
0.8
+1
+1
170
190
40
8
0.5
-15
Max.
Unit
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
Automatic CE Power-Down Max. V
CC
, CE > V
IH
Current —TTL Inputs
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Automatic CE Power-Down Max. V
CC
, CE > V
CC
– 0.3V, Com’l/Ind’l
Current —CMOS Inputs
V
IN
> V
CC
– 0.3V,or
Com’l L
V
IN
< 0.3V, f = 0
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
AC Test Loads and Waveforms
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
351Ω
R1 317Ω
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
ALL INPUT PULSES
3.3V
90%
GND
Rise time: 1 V/ns
10%
90%
10%
Fall time:
1 V/ns
(b)
(a)
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06434 Rev. **
Page 2 of 8
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CY7C1041BNV33
Switching Characteristics
[4]
Over the Operating Range
-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
-15
Max.
Min.
15
12
15
3
12
6
15
7
0
6
7
3
6
7
0
12
6
15
7
0
6
7
15
12
12
0
0
12
8
0
3
6
7
12
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
12
3
0
3
0
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
Byte Enable to End of Write
10
12
10
10
0
0
10
7
0
3
0
WRITE CYCLE
[7, 8]
Data Retention Characteristics
Over the Operating Range
(For L version only)
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[9]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Conditions
[10]
Min.
2.0
330
0
t
RC
Max.
Unit
V
µA
ns
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
9. t
r
< 3 ns for the -12 and -15 speeds.
10. No input may exceed V
CC
+ 0.5V.
Document #: 001-06434 Rev. **
Page 3 of 8
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CY7C1041BNV33
Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
3.0V
t
CDR
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
I
CC
I
SB
t
HZOE
HIGH
IMPEDANCE
DATA OUT
Notes:
11. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
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