5962F9671201VCC datasheet, PDF

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5962F9671201VCC: DescriptionACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14; Categorylogic logic; File Size100KB，3 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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5962F9671201VCC Overview

ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14

5962F9671201VCC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	_compli
Other features	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY
series	ACT
JESD-30 code	R-CDIP-T14
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	INVERTER
MaximumI(ol)	0.008 A
Number of functions	6
Number of entries	1
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Prop。Delay @ Nom-Su	14 ns
propagation delay (tpd)	14 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	MIL-PRF-38535 Class V
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
total dose	300k Rad(Si) V
width	7.62 mm
Base Number Matches	1

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ACTS04MS

January 1996

Radiation Hardened

Hex Inverter

Pinouts

14 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835

DESIGNATOR CDIP2-T14, LEAD FINISH C

TOP VIEW

A1 1

Y1 2

A2 3

Y2 4

A3 5

Y3 6

GND 7

14 VCC

13 A6

12 Y6

11 A5

10 Y5

9 A4

8 Y4

Features

• Devices QML Qualiﬁed in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in

SMD# 5962-96712 and Intersil’s QM Plan

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x 10

-10

Errors/Bit/Day

(Typ)

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm

/mg

• Dose Rate Upset . . . . . . . . . . . . . . . . >10

RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability . . . . . . . . . . . >10

RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55

C to +125

• Signiﬁcant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current

≤

1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . . . 14ns (Max), 9ns (Typ)

14 PIN CERAMIC FLATPACK MIL-STD-1835

DESIGNATOR CDFP3-F14, LEAD FINISH C

TOP VIEW

GND

VCC

TRUTH TABLE

Description

The Intersil ACTS04MS is a Radiation Hardened Hex Inverter.

The ACTS04MS utilizes advanced CMOS/SOS technology to achieve

high-speed operation. This device is a member of radiation hardened,

high-speed, CMOS/SOS Logic Family.

The ACTS04MS is supplied in a 14 lead Ceramic Flatpack (K sufﬁx) or a

Ceramic Dual-In-Line Package (D sufﬁx).

INPUTS

OUTPUTS

NOTE: L = Logic Level Low, H = Logic level High

Functional Diagram

Ordering Information

PART NUMBER

5962F9671201VCC

5962F9671201VXC

ACTS04D/Sample

ACTS04K/Sample

ACTS04HMSR

TEMPERATURE RANGE

-55

C to +125

-55

C to +125

SCREENING LEVEL

MIL-PRF-38535 Class V

Sample

Die

PACKAGE

14 Lead SBDIP

14 Lead Ceramic Flatpack

14 Lead SBDIP

14 Lead Ceramic Flatpack

Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

Spec Number

File Number

518782

3383.1

5962F9671201VCC Related Products

	5962F9671201VCC	5962F9671201VXC
Description	ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14	ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14, CERAMIC, DFP-14
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	DIP	DFP
package instruction	DIP, DIP14,.3	DFP, FL14,.3
Contacts	14	14
Reach Compliance Code	_compli	not_compliant
Other features	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHNOLOGY
series	ACT	ACT
JESD-30 code	R-CDIP-T14	R-CDFP-F14
JESD-609 code	e0	e0
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	INVERTER	INVERTER
MaximumI(ol)	0.008 A	0.008 A
Number of functions	6	6
Number of entries	1	1
Number of terminals	14	14
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DFP
Encapsulate equivalent code	DIP14,.3	FL14,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V
propagation delay (tpd)	14 ns	14 ns
Certification status	Not Qualified	Not Qualified
Schmitt trigger	NO	NO
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
Maximum seat height	5.08 mm	2.92 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	NO	YES
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	FLAT
Terminal pitch	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
total dose	300k Rad(Si) V	300k Rad(Si) V
width	7.62 mm	6.285 mm
Base Number Matches	1	1

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