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CAT5269U-00TE13

Description
Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface
Categoryaccessories   
File Size94KB,18 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet View All

CAT5269U-00TE13 Overview

Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface

CAT5419
Dual Digitally Programmable Potentiometers (DPP™) with
64 Taps and 2-wire Interface
FEATURES
s
Two linear-taper digital potentiometers
s
64 resistor taps per potentiometer
s
End-to-end resistance 2.5k
, 10k
, 50k
or 100k
s
Potentiometer control and memory access via
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Recall of wiper settings at power up
s
2.5 to 6.0 volt operation
s
Standby current less than 1
µ
A
s
1,000,000 nonvolatile WRITE cycles
s
100 year nonvolatile memory data retention
s
24-lead SOIC, 24-lead TSSOP and BGA
s
Write protection for data register
2-wire interface (I C like)
s
Low wiper resistance, typically 80Ω
s
Four non-volatile wiper settings for each
2
potentiometer
DESCRIPTION
The CAT5419 is two Digitally Programmable
Potentiometers (DPP™) integrated with control logic
and 16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP. Associated
with each wiper control register are four 6-bit non-
volatile memory data registers (DR) used for storing up
to four wiper settings. Writing to the wiper control register
or any of the non-volatile data registers is via a 2-wire
serial bus (I
2
C-like). On power-up, the contents of the
first data register (DR0) for each of the two potentiometers
is automatically loaded into its respective wiper control
registers (WCR).
The Write Protection (WP) pin protects against
inadvertent programming of the data register.
The CAT5419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (J, W)
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT
19
5419
18
17
16
15
14
13
1
A
B
RW0
RL0
VCC
NC
NC
NC
NC
NC
NC
NC
A0
NC
A3
SCL
NC
NC
NC
NC
2
A2
WP
RH0
NC
NC
A0
SDA
A1
RL1
RH1
RW1
GND
NC
NC
NC
NC
SCL
A3
3
A1
SDA
RH1
NC
A3
SCL
TSSOP Package (U, Y)
1
2
3
4
5
6
7
8
9
10
11
12
4
RL1
RW1
VSS
NC
NC
NC
24
23
22
21
20
CAT
19
5419
18
17
16
15
14
13
WP
A2
RW0
RH0
RL0
VCC
NC
NC
NC
NC
A0
NC
FUNCTIONAL DIAGRAM
RH0
RH1
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R W0
WP
R W1
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0
RL1
BGA
C
D
E
F
Top View - Bump Side Down
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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