ADE-203-260A (Z)
HM514260C/CL Series
HM51S4260C/CL Series
262,144-word
×
16-bit Dynamic Random Access Memory
Rev. 1.0
Jun. 12, 1995
The Hitachi HM51(S)4260C/CL are CMOS
dynamic RAM organized as 262,144-word
×
16-
bit. HM51(S)4260C/CL have realized higher
density, higher performance and various functions
by employing 0.8 µm CMOS process technology
and some new CMOS circuit design technologies.
The HM51(S)4260C/CL offer Fast Page Mode as a
high speed access mode. Multiplexed address
input permits the HM51(S)4260C/CL to be
packaged in standard 400-mil 40-pin plastic SOJ,
standard 475-mil 40-pin plastic Zip and standard
400-mil 44-pin plastic TSOP II. Internal refresh
timer enables HM51S4260C/CL self refresh
operation.
Features
• Single 5 V (±10%)
• High speed
— Access time:
60 ns/70 ns/80 ns (max)
• Low power dissipation
— Active mode:
825 mW/770 mW/688 mW (max)
— Standby mode 11 mW (max)
1.1 mW (max) (L-version)
• Fast page mode capability
• 512 refresh cycles: 8 ms
128 ms (L-version)
• 2CAS byte control
• 2 variations of refresh
—
RAS-only
refresh
—
CAS-before-RAS
refresh
• Battery back up operation (L-version)
• Self refresh operation (HM51S4260C/CL)
HM514260C/CL, HM51S4260C/CL Series
Ordering Information
Type No.
HM514260CJ-6
HM514260CJ-7
HM514260CJ-8
HM514260CZ-6
HM514260CZ-7
HM514260CZ-8
HM514260CTT-6
HM514260CTT-7
HM514260CTT-8
HM514260CLJ-6
HM514260CLJ-7
HM514260CLJ-8
HM514260CLZ-6
HM514260CLZ-7
HM514260CLZ-8
HM514260CLTT-6
HM514260CLTT-7
HM514260CLTT-8
Access
time
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
Package
400-mil 40-pin
plastic SOJ
(CP-40DA)
475-mil 40-pin
plastic ZIP
(ZP-40)
400-mil 44-pin
plastic TSOP II
(TTP-44/40DB)
400-mil 40-pin
plastic SOJ
(CP-40DA)
475-mil 40-pin
plastic ZIP
(ZP-40)
400-mil 44-pin
plastic TSOP II
(TTP-44/40DB)
Type No.
HM51S4260CJ-6
HM51S4260CJ-7
HM51S4260CJ-8
HM51S4260CTT-6
HM51S4260CTT-7
HM51S4260CTT-8
HM51S4260CLJ-6
HM51S4260CLJ-7
HM51S4260CLJ-8
HM51S4260CLTT-6
HM51S4260CLTT-7
HM51S4260CLTT-8
Access
time
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
Package
400-mil 40-pin
plastic SOJ
(CP-40DA)
400-mil 44-pin
plastic TSOP II
(TTP-44/40DB)
400-mil 40-pin
plastic SOJ
(CP-40DA)
400-mil 44-pin
plastic TSOP II
(TTP-44/40DB)
2
HM514260C/CL, HM51S4260C/CL Series
Pin Arrangement
HM514260CJ/CLJ Series
HM51S4260CJ/CLJ Series
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
HM514260CZ/CLZSeries
I/O9 2
I/O11 4
I/O12 6
I/O14 8
V
SS
10
I/O0 12
I/O2 14
V
CC
16
I/O5 18
I/O7 20
22
NC
RAS 24
26
A0
28
A2
V
CC
30
32
A4
34
A6
36
A8
UCAS 38
40
NC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
I/O8
I/O10
V
SS
I/O13
I/O15
V
CC
I/O1
I/O3
I/O4
I/O6
NC
WE
NC
A1
A3
V
SS
A5
A7
OE
LCAS
(Top View)
(Bottom View)
HM514260CTT/CLTT Series
HM51S4260CTT/CLTT Series
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
Pin Description
Pin name
A0 to A8
Function
Address input
–
–
–
I/O0 to I/O15
RAS
UCAS, LCAS
WE
OE
V
CC
V
SS
Row address
A0 to A8
Column address A0 to A8
Refresh address A0 to A8
Data-in/data-out
Row address strobe
Column address strobe
Read/write enable
Output enable
Power (+5 V)
Ground
NC
NC
WE
RAS
NC
A0
A1
A2
A3
V
CC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
(Top View)
3
HM514260C/CL, HM51S4260C/CL Series
Block Diagram
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
Selector
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
Row
Decoder
Row
Row
Decoder
Decoder
Row
Decoder
Row
Decoder
Row
Row
Decoder
Decoder
Row
Decoder
Selector
Selector
Selector
I/O4
I/O4
Buffer
I/O5
Buffer
I/O6
Buffer
I/O7
Buffer
256 k Memory Array Mat
I/O11
Buffer
Peripheral Circuit
I/O3
I/O3
Buffer
I/O2
I/O2
Buffer
I/O1
I/O1
Buffer
I/O0
I/O0
Buffer
I/O15
I/O15
Buffer
I/O14
I/O14
Buffer
I/O13
I/O13
Buffer
I/O12
I/O12
Buffer
I/O11
I/O5
I/O10
I/O10
Buffer
I/O9
Buffer
I/O8
Buffer
I/O9
I/O6
I/O7
I/O8
Peripheral Circuit
WE
RAS
Address
A0,A1,A2,A3
Address A4,A5
A6,A7,A8
LCAS
UCAS
OE
Selector
Row
Decoder
Selector
Row
Decoder
Selector
Row
Decoder
Selector
Row
Decoder
Row
Row
Decoder
Decoder
Row
Row
Decoder
Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
4
256 k Memory Array Mat
Peripheral Circuit
HM514260C/CL, HM51S4260C/CL Series
Operation Mode
The HM51(S)4260C/CL series has the following 11 operation modes.
1.
2.
3.
4.
5.
6.
Read cycle
Early write cycle
Delayed write cycle
Read- modify-write cycle
RAS-only
refresh cycle
CAS-before-RAS
refresh cycle
7.
8.
Self refresh cycle (HM51S4260C/CL)
Fast page mode read cycle
9. Fast page mode early write cycle
10. Fast page mode delayed write cycle
11. Fast page mode read- modify-write cycle
Inputs
RAS
H
H
L
L
L
L
L
H to L
LCAS
H
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H to L
H to L
H to L
H to L
L
UCAS
H
L
L
L
L
L
H
L
H
L
H to L
H to L
H to L
H to L
L
H
L
*2
L
*2
H to L
H
L
D
H
L to H
H
Valid
Open
Undefined
Valid
Open
Fast page mode read cycle
Fast page mode early write cycle
Fast page mode delayed write cycle
Fast page mode read-modify-write
cycle
Read cycle (Output disabled)
WE
D
H
H
L
*2
L
*2
H to L
D
D
OE
D
L
L
D
H
L to H
D
D
Output
Open
Valid
Valid
Open
Undefined
Valid
Open
Open
Operation
Standby
Standby
Read cycle
Early write cycle
Delayed write cycle
Read-modify-write cycle
RAS-only
refresh cycle
CAS-before-RAS
refresh cycle
Self refresh cycle (HM51S4260C/CL)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. t
WCS
≥
0 ns Early write cycle
t
WCS
< 0 ns Delayed write cycle
3. Mode is determined by the OR function of the
UCAS
and
LCAS.
(Mode is set by the earliest of
UCAS
and
LCAS
active edge and reset by the latest of
UCAS
and
LCAS
inactive edge.)
However write OPERATION and output HIZ control are done independently by each
UCAS,
LCAS.
ex. if
RAS
= H to L,
LCAS
= L,
UCAS
= H, then
CAS-before-RAS
refresh cycle is selected.
5