while covering a wide frequency output range up to
800MHz, without the use of external components.
The high performance and high frequency output is
achieved using a low cost fundamental crystal of
between 19MHz and 44 MHz. The PL685 family is
designed to address the demanding requirements of
high performance applications such Fiber Channel,
serial ATA, Ethernet, SAN, SONET/SDH, etc.
OUTPUT ENABLE CONTROL
OE Select
(Programmable)
0
1 (Default)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
BLOCK DIAGRAM
OE/PDB
(Default pre-programmed output path)
XIN/REF
XOUT
Xtal
Osc
PD/CP
LF – HF
LCVCOs
Pre-scalar
4/6
/2
Q
QB
M Divider
(5 bit)
P Divider
(4 bit)
/2
Programmable Function
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/16/11 Page 1
(Preliminary)
PL685-XX
19MHz to 800MHz Low Phase-Noise XO
PIN ASSIGNMENT
Name
XIN
DNC
OE/PDB
GND_ANA
GND_DIG
GND_BUF
Q
QB
VDD_BUF
VDD_DIG
VDD_ANA
XOUT
Pin #
1
2, 3, 5, 9
4
6
7
8
10
12
11, 13
14
15
16
Type
I
-
I
P
P
P
O
O
P
P
P
P
Crystal input connection.
Do Not Connect.
This pin may be programmed as output enable (OE), or power -down
(PDB) pin. This pin incorporates an Internal pull -up resistor of 60KΩ
for OE, and PDB, operations.
GND connection for analog circuitry.
GND connection for digital circuitry.
GND connection for buffer circuitry.
True Output buffer.
Complementary Output buffer.
VDD connection for buffer circuitry.
VDD connection for digital circuitry.
VDD connection for analog circuitry.
Output connection to crystal.
Description
OPTION SELECTION TABLE
PL685 is a fully programmable clock IC. However, for ordering convenience, the following part numbers have
been created for when simple multiplication is used, for your convenience. When other features of the IC are
exercised (i.e. reverse polarity on OE, power down, etc.), a nother 3-digit code is used to identify the functionality.
Input Crystal
Frequency Range (MHz)
33.750000 ~ 40.000000
33.333333 ~ 42.187500
32.142857 ~ 38.095238
33.333333 ~ 37.500000
33.750000 ~ 40.000000
33.333333 ~ 42.187500
32.142857 ~ 38.095238
33.333333 ~ 37.500000
33.750000 ~ 40.000000
33.333333 ~ 42.187500
32.142857 ~ 38.095238
33.333333 ~ 37.500000
33.750000 ~ 40.000000
32.812500 ~ 42.187500
Multiplication
Factor
X20
X16
X14
X12
X10
X8
X7
X6
X5
X4
X3.5
X3
X2.5
X2
Output Frequency Range (MHz)
Low Limit
High Limit
675.00
800.00
533.33
675.00
450.00
533.33
400.00
450.00
337.50
400.00
266.67
337.50
225.00
266.67
200.00
225.00
168.75
200.00
133.33
168.75
112.50
133.33
100.00
112.50
84.375
100.00
65.625
84.375
Part #
PL685-P8-020
PL685-P8-168
PL685-P8-148
PL685-P8-128
PL685-P8-108
PL685-P8-088
PL685-P8-078
PL685-P8-068
PL685-P8-058
PL685-P8-048
PL685-P8-358
PL685-P8-038
PL685-P8-258
PL685-P8-028
Common functionality for packaged parts in the above table:
OE function active high polarity.
Crystal Cload is 12pF.
Please inform your Sales representative for active low OE functionality.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/16/11 Page 2
(Preliminary)
PL685-XX
19MHz to 800MHz Low Phase-Noise XO
FUNCTIONAL DESCRIPTION
PL685 family of products is an advanced,
programmable LCVCO clock IC that is designed to
meet the most stringent performance specifications
for phase noise, jitter, and power consumption.
There are two main types of VCOs, a) Ring
Oscillator, b) LC Tank oscillator. An LCVCO is made
up of LC tank oscillator. Although a Ring Oscillator
has very good performance, and has a good tuning
range, its phase noise and jitter performance, in
particular at higher frequencies, degrades.
On the other hand, an LCVCO has an outstanding
phase noise and jitter performance, even at higher
frequencies. PL685 family of products takes
advantage of this state of the art technology, and
incorporates the LC tank on-chip, for optimal
performance.
PL685 family exhibit very low phase noise/phase
jitter and peak to peak jitter, wide tuning range, and
very low-power. All members of the PL685 family
accept a low-cost fundamental crystal input of
19MHz to 44MHz or a reference clock input of up to
800MHz and its flexible core is capable of producing
any output frequency between 19MHz to 800MHz.
PLL Programming
The PLL in the PL685 family is fully programmable.
The PLL is equipped with a Prescaler to divide down
the VCO frequency, and a 5-bit VCO frequency
feedback loop divider (M-Counter). The output of the
PLL is transferred to a 4-bit post VCO divider (P-
Counter), to achieve the desired output frequency.
OE (Output Enable)
The OE pin in PL685 family, through programming,
can be configured to support OE pin activation with a
logic ‘1’ or logic ’0’, to provide you with the desired
enable polarity.
OE Select
(Programmable)
0
1 (Default)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
The OE pin incorporates a 60K
Ω
resistor to either
pull-up or pull-down to the default state when the OE
pin is left open.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/16/11 Page 3
(Preliminary)
PL685-XX
19MHz to 800MHz Low Phase-Noise XO
ELECTRICAL SPECIFICATIONS
1. ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature (industrial temperature)*
Ambient Operating Temperature (commercial temperature)
Junction Temperature
ESD Protection, Machine Model
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
AI
T
AC
T
J
200
2
-0.5
-0.5
-65
-40
0
MIN
MAX
4.6
V
DD
+0.5
V
DD
+0.5
150
85
70
125
UNITS
V
V
V
C
C
C
C
V
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the
device and affect product reliability. These co nditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to
commercial grade only.
2. GENERAL ELECTRICAL SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic
Supply Current, Dynamic
PDB Enabled
Output Enable Time
Power Up Time
Operating Voltage
Power Up Ramp Rate
Auto-Calibration Time
Output Clock Duty Cycle
t
OE
T
PU
V
DD
t
PU
t
AC
SYMBOL
I
DDQ
CONDITIONS
LVPECL, 622.08MHz, 3.3V
PDB = 0, 3.3V
OE logic 0 to logic 1, Ta=25º C.
Add one clock period to this
measurement for a usable clock
output.
PDB logic 0 to logic 1, Ta=25º C
LVPECL
Time for V
DD
to reach 90% V
DD
.
Power ramp must be monotonic.
At power up
@ 50% of output waveform
2.97
0.1
MIN
TYP
MAX
90
10
50
10
3.63
100
10
45
50
55
UNITS
mA
uA
ns
ms
V
ms
ms
%
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 09/16/11 Page 4
(Preliminary)
4. CRYSTAL SPECIFICATIONS
PARAMETERS
Crystal Resonator Frequency
Crystal Cload
Shunt Capacitance
Recommended ESR
SYMBOL
F
XIN
C
L_ Crys ta l
C
0_ Crys ta l
R
E
AT cut , up to 40MHz
AT cut , up to 44MHz
CONDITIONS
Parallel Fundamental Mode
V
DD
= 3.3V, programmable
MIN
19
8
PL685-XX
TYP
MAX
44
12
3.5
50
45
UNITS
MHz
pF
pF
Ω
Ω
19MHz to 800MHz Low Phase-Noise XO
5. JITTER SPECIFICATIONS
PARAMETERS
RMS Phase Jitter
Period Jitter, Pk-to-Pk
FREQUENCY
622.08MHz
622.08MHz
CONDITIONS
12kHz to 20MHz, XIN=38.88MHz
10K cycles, XIN=38.88MHz
MIN
TYP
MAX
0.5
30
UNITS
ps
ps
6. PHASE NOISE SPECIFICATIONS
PARAMETERS
Phase Noise, relative
to carrier (typical)
FREQUENCY
155.52MHz
622.08MHz
@10Hz
-61
-46
@100Hz
-90
-77
@1kHz
-114
-101
@10kHz
-123
-111
@100kHz
-126
-114
UNITS
dBc/Hz
7. LVPECL OUTPUTS (Q, QB)
PARAMETERS
SYMBOL
Output High Voltage
Output Low Voltage
Output Frequency
Output Rise, Fall Times
Output Voltage Swing
LVPECL Levels Test Circuit
CONDITIONS
Q, QB
Standard LVPECL Termination,
V
DD
= 3.3V
3.3V
20% - 80% of output waveform
Q, QB
MIN
2.275
1.490
19
550
TYP
2.350
1.600
300
800
MAX
2.420
1.680
800
500
930
UNITS
V
V
MHz
ps
mV
V
OH
V
OL
F
ou t
t
r
, t
f
V
pp
LVPECL Transistion Time Waveform
DUTY CYCLE
OUT
VDD
45 - 55%
55 - 45%
50?
2.0V
OUT
80%
50%
50?
20%
OUT
OUT
t
R
t
F
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
京公网安备 11010802033920号
EEWORLD
