570NCC000112DG datasheet, PDF - EEWORLD Datasheet

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570NCC000112DG: Descriptionstandard clock oscillators progrmable XO 8 pin 0.3ps RS jtr (ncnr); CategoryPassive components; File Size585KB，36 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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570NCC000112DG Overview

standard clock oscillators progrmable XO 8 pin 0.3ps RS jtr (ncnr)

570NCC000112DG Parametric

Parameter Name	Attribute value
Manufacture	Silicon Laboratories
Product Category	Standard Clock Oscillators
RoHS	Yes

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Si 5 7 0 / S i 5 7 1

10 MH

Features



1.4 G H

C P

ROGRAMMABLE

XO/VCXO

Any programmable output



frequencies from 10 to 945 MHz and

select frequencies to 1.4 GHz



C serial interface



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available LVPECL, CMOS,

LVDS, and CML outputs

Industry-standard 5x7 mm

package

Pb-free/RoHS-compliant



1.8, 2.5, or 3.3 V supply

Si5602

Applications



Ordering Information:



SONET/SDH

xDSL

10 GbE LAN/WAN

ATE

High performance

instrumentation



Low-jitter clock generation



Optical modules



Clock and data recovery

See page 31.

Pin Assignments:

See page 30.

(Top View)

SDA

Description

The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-

programmable to any output frequency from 10 to 945 MHz and select frequencies

to 1400 MHz with <1 ppb resolution. The device is programmed via an I

C serial

interface. Unlike traditional XO/VCXOs where a different crystal is required for

each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL

clock synthesis IC to provide any-frequency operation. This IC-based approach

allows the crystal resonator to provide exceptional frequency stability and

reliability. In addition, DSPLL clock synthesis provides superior supply noise

rejection, simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems.

CLK–

GND

SCL

CLK+

Functional Block Diagram

CLK-

CLK+

Si570

SDA

Fixed

Frequency

10-1400 MHz



DSPLL Clock

Synthesis

SDA

SCL

CLK–

Si571 only

ADC

GND

SCL

CLK+

GND

Si571

Si570/Si571

Rev. 1.6 6/18

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