DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC1663
DC to VHF WIDEBAND DIFFERENTIAL INPUT AND OUTPUT AMPLIFIER IC
DESCRIPTION
The
µ
PC1663 is a differential input, differential output wideband amplifier IC that uses an high frequency silicon
bipolar process. This process improves bandwidth phase characteristics, input noise voltage characteristics, and low
power consumption when compared to conventional HF-band differential amplifier ICs.
These features make this device suitable as a wideband amplifier in high-definition TVs, high-resolution monitors,
broadcasting satellite receivers, and video cameras, as a sense amplifier in high-density CCD and optical pick-up
products, or as a pulse amplifier for optical data links.
TM
These ICs are manufactured using NEC’s 6 GHz f
T
NESAT I silicon bipolar process. This process uses silicon
nitride passivation film and gold electrodes. These materials can protect chip surface from external pollution and
prevent corrosion/migration. Thus, these ICs have excellent performance, uniformity and reliability.
FEATURES
• Bandwidth and typical gain : 120 MHz @ A
VOL
= 300
700 MHz @ A
VOL
= 10
• Phase delay
• Input Noise Voltage
• Supply Current
: –85 deg. @ A
VOL
= 100, 100 MHz
: 3
µ
V
r.m.s.
(R
S
= 50
Ω,
10 k to 10 MHz)
: 13mA TYP. @ V
CC
±
=
±6
V
• Gain adjustable from 10 to 300 with external resistor
• No frequency compensation required (Small phase delay at 10 MHz or less)
ORDERING INFORMATION
Part Number
Package
8-pin plastic SOP (225 mil)
Marking
1663
Supplying Form
Embossed tape 12 mm wide.
Pin 1 is in tape pull-out direction.
Qty 2.5 kp/reel.
Embossed tape 8 mm wide.
Pin 1 is in tape pull-out direction.
Qty 1 kp/reel.
µ
PC1663G-E1
µ
PC1663GV-E1
8-pin plastic SSOP (175 mil)
Remark
To order evaluation samples, please contact your local NEC sales office. (Part number for sample order:
µ
PC1663G,
µ
PC1663GV)
Caution
µ
PC1663C (8-pin plastic DIP) is discontinued.
Caution Electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G11024EJ6V0DS00 (6th edition)
Date Published September 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1987, 1999
µ
PC1663
CONNECTION DIAGRAM
(Top View)
1
8
Pin No.
1
2
Pin Name
IN
2
G
1B
V
CC
−
OUT
2
OUT
1
V
CC
+
2
7
3
4
5
3
6
4
5
6
7
8
G
1A
IN
1
PIN EXPLANATIONS
In Dual
Bias
(V)
Pin
voltage
0
Pin
voltage
0
±2
to
±6.5
In Single
Bias
(V)
Apply
voltage
V
CC
/2
Apply
voltage
V
CC
/2
–0.3 to +14
Pin
No.
8
1
5
4
6
Pin
Name
IN
1
IN
2
OUT
1
OUT
2
V
CC
+
Functions and Applications
Internal Equivalent Circuit
Input pin
6
Output pin
Plus voltage supply pin.
This pin should be
connected with bypass
capacitor to minimize AC
impedance.
Minus voltage supply pin.
This pin should be
connected with bypass
capacitor to minimize AC
impedance.
Gain adjustment pin.
External resistor from 0 to
10 kΩ can be inserted
between pin 2 and 7 to
determine gain value.
8
7
Note
1
2
Note
5
4
(G
2A
)
(G
2B
)
3
V
CC
–
GND
3
7
2
G
1A
G
1B
—
—
Internal circuit constants should be referred to
application note.
Note
µ
PC1664 which had G
2A
, G
2B
of the other gain adjustment pins is discontinued.
2
Data Sheet G11024EJ6V0DS00
µ
PC1663
ABSOLUTE MAXIMUM RATINGS (T
A
= +25 °C)
Parameter
Supply Voltage
Power Dissipation
Differential Input Voltage
Input Voltage
Symbol
V
CC
±
P
D
V
ID
V
ICM
(within V
CC
Output Current
Operating Ambient Temperature
Storage Temperature
I
O
T
A
T
stg
−
µ
PC1663G
±7
280 (T
A
= +75°C)
±5
±6
+
to V
CC
range)
35
−45
to
+75
−55
to
+150
Note
µ
PC1663GV
±7
280 (T
A
= +75
°C)
±5
−
Note
Unit
V
mW
V
V
(within V
CC
±6
+
to V
CC
range)
35
mA
°C
°C
−45
to
+75
−55
to
+150
Note
Mounted on double sided copper clad 50
×
50
×
1.6 mm epoxy glass PWB
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Output Source Current
Output Sink Current
Operating Frequency Range
Symbol
V
CC
±
I
O source
I
O sink
f
opt
MIN.
±2
—
—
DC
TYP.
±6
—
—
—
MAX.
±6.5
20
2.5
200
Unit
V
mA
mA
MHz
Data Sheet G11024EJ6V0DS00
3
µ
PC1663
TEST CIRCUIT
50
Ω
50
Ω
1
2
8
7
6
5
0.1
µ
F
950
Ω
0.1
µ
F
1 000 pF
IN
Z
S
= 50
Ω
1 000 pF
V
CC
–
0.1
µ
F
1 kΩ
3
4
V
CC+
OUT
Z
L
=
50
Ω
Remark
Measurement value at
OUT connector should
be converced into DUT’s
output value at pin 5.
Remark
Definition and test circuit of each characteristic should be referred to application note ‘Usage of
µ
PC1663 (Document No. G12290E)’.
NOTES ON CORRECT USE
(1)
(2)
(3)
(4)
(5)
Observe precautions for handling because of electro-static sensitive devices.
Form a ground pattern as wide as possible to minimize ground impedance (to prevent undesired
oscillation).
The bypass capacitor should be attached to V
CC
line.
When gain between Gain 1 and Gain 2 is necessary, insert adjustment resistor (0 to 10 kΩ) between
Ω
G
1A
and G
1B
to determine gain value.
Due to high-frequency characteristics, the physical circuit layout is very critical. Supply voltage line
bypass, double-sided printed-circuit board, and wide-area ground line layout are necessary for stable
operation. Two signal resistors connected to both inputs and two load resistors connected to both
outputs should be balanced for stable operation.
V
CC+
50
Ω
50
Ω
V
CC–
(150
Ω
to
∞)
(150
Ω
to
∞)
Data Sheet G11024EJ6V0DS00
5
FPGA/CPLD
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