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PSD913F1V-15J

Description
256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size375KB,94 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric View All

PSD913F1V-15J Overview

256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52

PSD913F1V-15J Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeQFN
package instructionPLASTIC, LDCC-52
Contacts52
Reach Compliance Code_compli
ECCN codeEAR99
Maximum access time1.5e-7 ns
JESD-30 codeS-PQCC-J52
JESD-609 codee0
length19.1262 mm
Number of I/O lines27
Number of ports4
Number of terminals52
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC52,.8SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3 V
Certification statusNot Qualified
ROM size (bits)1310720 Bits
Maximum seat height4.57 mm
Maximum standby current0.0001 A
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
UV erasableN
width19.1262 mm
uPs/uCs/peripheral integrated circuit typePARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches1
PSD913F2
PSD934F2 PSD954F2
Flash In-System Programmable (ISP) Peripherals
For 8-bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY
s
Single Supply Voltage:
– 5 V±10% for PSD9xxF2
– 3.3 V±10% for PSD9xxF2-V
s
Figure 1. Packages
Up to 2Mbit of Primary Flash Memory (8 uniform
sectors)
256Kbit Secondary Flash Memory (4 uniform
sectors)
Up to 256Kbit SRAM
Over 2,000 Gates of PLD: DPLD
27 Reconfigurable I/O ports
Enhanced JTAG Serial Port
Programmable power management
High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Erase/Write Cycles of PLD
PQFP52 (T)
s
s
s
s
s
s
s
PLCC52 (K)
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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