Low Voltage, Low Skew,
PCI / PCI-X Clock Generator
Datasheet
8761I
Description
The 8761I is a low voltage, low skew PCI / PCI-X clock generator.
The device has a selectable REF_CLK or crystal input. The
REF_CLK input accepts LVCMOS or LVTTL input levels. The
8761I has a fully integrated PLL along with frequency configurable
clock and feedback outputs for multiplying and regenerating
clocks with “zero delay” Using a 20MHz or 25MHz crystal or a
33.333MHz or 66.666MHz reference frequency, the 8761I will
generate output frequencies of 33.333MHz, 66.666MHz, 100MHz
and 133.333MHz simultaneously.
The low impedance LVCMOS/LVTTL outputs of the 8761I are
designed to drive 50Ω series or parallel terminated transmission
lines.
Features
▪
Fully integrated PLL
▪
Seventeen LVCMOS/LVTTL outputs, 15Ω typical output
impedance
▪
Selectable crystal oscillator interface or LVCMOS/LVTTL
REF_CLK
▪
Maximum output frequency: 166.67MHz
▪
Maximum crystal input frequency: 40MHz
▪
Maximum REF_CLK input frequency: 83.33MHz
▪
Individual banks with selectable output dividers for generating
33.333MHz, 66.66MHz, 100MHz and 133.333MHz
simultaneously
▪
Separate feedback control for generating PCI / PCI-X
frequencies from a 20MHz or 25MHz crystal or 33.333MHz or
66.666MHz reference frequency
▪
Cycle-to-cycle jitter: 70ps (maximum)
▪
Period jitter, RMS: 17ps (maximum)
▪
Output skew: 250ps (maximum)
▪
Bank skew: 50ps (maximum)
▪
Static phase offset: 0 ± 150ps (maximum)
▪
Full 3.3V or 3.3V core, 2.5V multiple output supply modes
▪
-40°C to 85°C ambient operating temperature
▪
Available in both standard and lead-free RoHS-compliant
packages
Block Diagram
©2017 Integrated Device Technology, Inc.
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8761I Datasheet
Pin Assignments
Figure 1. 10mm x 10mm x 1.4mm, 64-Lead TQFP (Top View
Table 1. Pin Descriptions
Number
1
2, 16, 17, 21,
25, 29, 33,
48, 52, 56,
60, 64
3, 4
5, 9, 40, 44
6
7
8
10, 11
12
13
Name
REF_CLK
GND
Input
Type
[a]
Pulldown
Description
Reference clock input. LVCMOS / LVTTL interface levels.
Power supply ground.
Power
XTAL1, XTAL2
V
DD
XTAL_SEL
PLL_SEL
V
DDA
D_SELC0,
D_SELC1
OEC
OEA
Input
Power
Input
Input
Power
Input
Input
Input
Pulldown
Pullup
Pullup
Pullup
Pullup
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Core supply pins.
Selects between crystal oscillator or reference clock as the PLL reference
source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW.
LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL. When
LOW, selects reference clock. LVCMOS / LVTTL interface levels.
Analog supply pin. See Applications Note for filtering.
Selects divide value for Bank C outputs as described in
Table 3
. LVCMOS /
LVTTL interface levels.
Determines state of Bank C outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank A outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
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8761I Datasheet
Table 1. Pin Descriptions
Number
14, 15
18, 20,
22, 24
19, 23
26, 28,
30, 32
27, 31
34, 35
36
37
38, 39
Name
D_SELA0,
D_SELA1
QA0, QA1,
QA2, QA3
V
DDOA
QB0, QB1,
QB2, QB3
V
DDOB
D_SELB1,
D_SELB0
OEB
OED
D_SELD1,
D_SELD0
MR
Input
Type
[a]
Pulldown
Description
Selects divider value for Bank A outputs as described in
Table 3
. LVCMOS /
LVTTL interface levels.
Bank A clock outputs. 15Ω typical output impedance. LVCMOS / LVTTL
interface levels.
Output supply pins for Bank A outputs.
Bank B clock outputs. 15Ω typical output impedance. LVCMOS / LVTTL
interface levels.
Output supply pins for Bank B outputs.
Output
Power
Output
Power
Input
Input
Input
Input
Pulldown
Pullup
Pullup
Pulldown
Selects divider value for Bank B outputs as described in
Table 3
. LVCMOS /
LVTTL interface levels.
Determines state of Bank B outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank D outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank D outputs as described in
Table 3
. LVCMOS /
LVTTL interface levels.
Active HIGH Master reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in
Table 3
.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in
Table 3
.
LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with “zero delay”.
LVCMOS / LVTTL interface levels.
Output supply pin for FB_Out output.
Feedback output. Connect to FB_IN. 15Ù typical output impedance.
LVCMOS / LVTTL interface levels.
Bank D clock outputs. 15Ω typical output impedance. LVCMOS / LVTTL
interface levels.
Output supply pins for Bank D outputs.
Bank C clock outputs. 15Ω typical output impedance. LVCMOS / LVTTL
interface levels.
Output supply pins for Bank C outputs.
41
Input
Pulldown
42
43
45
46
47
49, 51,
53, 55
50, 54
57, 59,
61, 63
58, 62
FBDIV_SEL1
FBDIV_SEL0
FB_IN
V
DDOFB
FB_OUT
QD3, QD2,
QD1, QD0
V
DDOD
QC3, QC2,
QC1, QC0
V
DDOC
Input
Input
Input
Power
Output
Output
Power
Output
Power
Pulldown
Pullup
Pulldown
[a] Pullup and Pulldown refer to internal input resistors. See
Table 2
for typical values.
©2017 Integrated Device Technology, Inc.
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8761I Datasheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation
Capacitance (per output)
[a]
Test Conditions
Minimum
Typical
4
Maximum
51
51
Units
pF
kΩ
kΩ
pF
pF
Ω
V
DD
, V
DDA
= 3.465V;
V
DDOx
= 3.465V
V
DD
, V
DDA
= 3.465V;
V
DDOx
= 2.625V
9
11
15
R
OUT
Output Impedance
[a] V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, V
DDOD
, V
DDOFB
.
Table 3. Output Control Pin Function
Inputs
MR
1
0
X
OEA
1
1
0
OEB
1
1
0
OEC
1
1
0
OED
1
1
0
QA0:QA3
LOW
Active
HiZ
Outputs
QB0:QB3
LOW
Active
HiZ
QC0:QC3
LOW
Active
HiZ
QD0:QD3
LOW
Active
HiZ
Table 4. Operating Mode Function
Inputs
PLL_SEL
0
1
Operating Mode
Bypass
PLL
Table 5. PLL Input Function
Inputs
XTAL_SEL
0
1
PLL Input
REF_CLK
XTAL Oscillator
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8761I Datasheet
Table 6. Control Functions
Outputs
Inputs
[a]
Reference
Frequency
Range (MHz)
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
PLL_SEL = 1
Frequency
QX0:QX3
(MHz)
83.33 - 166.67
83.33 - 166.67
83.33 - 166.67
83.33 - 166.67
62.4 - 125
62.4 - 125
62.4 - 125
62.4 - 125
41.6 - 83.33
41.6 - 83.33
41.6 - 83.33
41.6 - 83.33
20.8 - 41.67
20.8 - 41.67
20.8 - 41.67
20.8 - 41.67
FB_OUT
(MHz)
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
41.6 - 83.33
20.83 - 41.67
15.62 - 31.25
12.5 - 25
D_SELx1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D_SELx0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FBDIV_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FBDIV_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QX0:QX3
x2
x4
x 5.33
x 6.67
x 1.5
x3
x4
x5
x1
x2
x 2.67
x 3.33
÷2
÷1
x 1.33
x 1.67
[a] D_SELX1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELX0 denotes D_SELA0, D_SELB0, D_ SELC0, and D_SELD0.
QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
©2017 Integrated Device Technology, Inc.
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