Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5642A
Rev. 3.1, 06/2012
MPC5642A
Qorivva MPC5642A
Microcontroller Data Sheet
208 MAPBGA
(17 x 17 mm)
176 LQFP
(24 × 24 mm)
324 TEPBGA
(23 × 23 mm)
• 150 MHz e200z4 Power Architecture core
– Variable length instruction encoding (VLE)
– Superscalar architecture with 2 execution units
– Up to 2 integer or floating point instructions per cycle
– Up to 4 multiply and accumulate operations per cycle
• Memory organization
– 2 MB on-chip flash memory with ECC and
read-while-write (RWW)
– 128 KB on-chip SRAM with standby functionality (32
KB) and ECC
– 8 KB instruction cache (with line locking), configurable
as 2- or 4-way
– 14 + 3 KB eTPU code and data RAM
– 4
4 crossbar switch (XBAR)
– 24-entry MMU
• Fail Safe Protection
– 16-entry Memory Protection Unit (MPU)
– CRC unit with 3 submodules
– Junction temperature sensor
• Interrupt
– Configurable interrupt controller (INTC) with
non-maskable interrupt (NMI)
– 64-channel eDMA
• Serial channels
– 3 eSCI modules
– 3 DSPI modules (2 of which support downstream Micro
Second Channel [MSC])
– 3 FlexCAN modules with 64 message buffers each
– 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or
single channel, 128 message objects, ECC
• 1 eMIOS
– 24 unified channels
• 1 eTPU2 (second generation eTPU)
—32 standard channels
•
•
•
•
•
•
•
•
•
– 1 reaction module (6 channels with 3 outputs per
channel)
2 enhanced queued analog-to-digital converters (eQADCs)
– Forty 12-bit input channels (multiplexed on 2 ADCs);
expandable to 56 channels with external multiplexers
– 6 command queues
– Trigger and DMA support
– 688 ns minimum conversion time
On-chip CAN/SCI Bootstrap loader with Boot Assist
Module (BAM)
Nexus: Class 3+ for core; Class 1 for eTPU
JTAG (5-pin)
Development Trigger Semaphore (DTS)
– EVTO pin for communication with external tool
Clock generation
– On-chip 4–40 MHz main oscillator
– On-chip FMPLL (frequency-modulated phase-locked
loop)
Up to 112 general purpose I/O lines
– Individually programmable as input, output or special
function
– Programmable threshold (hysteresis)
Power reduction modes: slow, stop, and standby
Flexible supply scheme
– 5 V single supply with external ballast
– Multiple external supply: 5 V, 3.3 V, and 1.2 V
© Freescale Semiconductor, Inc., 2009, 2010, 2012. All rights reserved.
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.5.1 e200z4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . .10
1.5.3 Enhanced direct memory access (eDMA) . . . . .10
1.5.4 Interrupt controller (INTC) . . . . . . . . . . . . . . . . .11
1.5.5 Memory protection unit (MPU). . . . . . . . . . . . . .11
1.5.6 Frequency-modulated phase-locked loop
(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.7 System integration unit (SIU). . . . . . . . . . . . . . .12
1.5.8 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.9 Static random access memory (SRAM) . . . . . .14
1.5.10 Boot assist module (BAM) . . . . . . . . . . . . . . . . .14
1.5.11 Enhanced modular input/output system
(eMIOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.5.12 Second generation enhanced time processing
unit (eTPU2) . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.13 Reaction module (REACM) . . . . . . . . . . . . . . . .16
1.5.14 Enhanced queued analog-to-digital converter
(eQADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.5.15 Deserial serial peripheral interface (DSPI) . . . .18
1.5.16 Enhanced serial communications interface
(eSCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5.17 Controller area network (FlexCAN) . . . . . . . . . .19
1.5.18 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.19 System timers . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.20 Software watchdog timer (SWT) . . . . . . . . . . . .21
1.5.21 Cyclic redundancy check (CRC) module . . . . . .21
1.5.22 Error correction status module (ECSM). . . . . . .22
1.5.23 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .22
1.5.24 Calibration bus interface . . . . . . . . . . . . . . . . . .22
1.5.25 Power management controller (PMC) . . . . . . . .22
1.5.26 Nexus port controller (NPC) . . . . . . . . . . . . . . .23
1.5.27 JTAG controller (JTAGC) . . . . . . . . . . . . . . . . . .23
1.5.28 Development trigger semaphore (DTS). . . . . . .23
Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . .23
2.1 176 LQFP pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.2 208 MAP BGA ballmap . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 324 TEPBGA ballmap. . . . . . . . . . . . . . . . . . . . . . . . . .26
2.4 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3
2.5 Signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.1 Parameter classification. . . . . . . . . . . . . . . . . . . . . . . . 55
3.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.1 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4 EMI (electromagnetic interference) characteristics . . . 61
3.5 Electrostatic discharge (ESD) characteristics . . . . . . . 62
3.6 Power management control (PMC) and power on
reset (POR) electrical specifications . . . . . . . . . . . . . . 62
3.6.1 Regulator example . . . . . . . . . . . . . . . . . . . . . . 65
3.6.2 Recommended power transistors. . . . . . . . . . . 66
3.7 Power up/down sequencing. . . . . . . . . . . . . . . . . . . . . 66
3.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . 67
3.9 I/O pad current specifications . . . . . . . . . . . . . . . . . . . 72
3.9.1 I/O pad V
RC33
current specifications . . . . . . . . 73
3.9.2 LVDS pad specifications. . . . . . . . . . . . . . . . . . 74
3.10 Oscillator and PLLMRFM electrical characteristics . . . 75
3.11 Temperature sensor electrical characteristics . . . . . . . 77
3.12 eQADC electrical characteristics . . . . . . . . . . . . . . . . . 77
3.13 Configuring SRAM wait states. . . . . . . . . . . . . . . . . . . 79
3.14 Platform flash controller electrical characteristics . . . . 80
3.15 Flash memory electrical characteristics . . . . . . . . . . . 80
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.16.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 82
3.17 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.17.1 Reset and configuration pin timing . . . . . . . . . . 86
3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 86
3.17.3 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.17.4 Calibration bus interface timing . . . . . . . . . . . . 95
3.17.5 External interrupt timing (IRQ pin) . . . . . . . . . . 99
3.17.6 eTPU timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.17.7 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.17.8 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.17.9 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . 107
3.17.10FlexCAN system clock source . . . . . . . . . . . . 108
Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 109
4.1.1 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.1.2 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . 112
4.1.3 324 TEPBGA . . . . . . . . . . . . . . . . . . . . . . . . . 114
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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MPC5642A Microcontroller Data Sheet, Rev. 3.1
2
Freescale Semiconductor
Introduction
1
1.1
Introduction
Document overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5642A series of
microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical
characteristics. For functional characteristics, refer to the device reference manual.
1.2
Description
This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive
transmission control applications.
It is compatible with devices in Freescale’s MPC5600 family and offers performance and capabilities beyond the MPC5632M
devices.
The microcontroller’s e200z4 host processor core is built on the Power Architecture
®
technology and designed specifically for
embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal
processing (DSP).
The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM
and a 2 MB internal flash memory.
For development, the device includes a calibration bus that is accessible only when using the Freescale VertiCal Calibration
System.
1.3
Device feature summary
Table 1. MPC5642A device feature summary
Feature
Process
Core
SIMD
VLE
Cache
Non-Maskable Interrupt (NMI)
MMU
MPU
Crossbar switch
Core performance
Windowing software watchdog
Core Nexus
SRAM
Flash
Flash fetch accelerator
128 KB
2 MB
4
128-bit
4
4
0–150 MHz
Yes
Class 3+
192 KB
4 MB
4
256-bit
MPC5642A
90 nm
e200z4
Yes
Yes
8 KB instruction
NMI and Critical Interrupt
24-entry
16-entry
5
4
MPC5644A
Table 1
summarizes the MPC5642A features and compares them to those of the MPC5644A.
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
3
PCB Design
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