Features
•
High Performance, Low Power AVR
®
8-Bit Microcontroller
•
Advanced RISC Architecture
– 54 Powerful Instructions – Most Single Clock Cycle Execution
– 16 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 12 MIPS Throughput at 12 MHz
Non-volatile Program and Data Memories
– 512/1024 Bytes of In-System Programmable Flash Program Memory
– 32 Bytes Internal SRAM
– Flash Write/Erase Cycles: 10,000
– Data Retention: 20 Years at 85
o
C / 100 Years at 25
o
C
Peripheral Features
– QTouch
®
Library Support for Capacitive Touch Sensing (1 Channel)
– One 16-bit Timer/Counter with Prescaler and Two PWM Channels
– Programmable Watchdog Timer with Separate On-chip Oscillator
– 4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only)
– On-chip Analog Comparator
Special Microcontroller Features
– In-System Programmable (at 5V, only)
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Supply Voltage Level Monitor with Interrupt and Reset
– Internal Calibrated Oscillator
I/O and Packages
– Four Programmable I/O Lines
– 6-pin SOT and 8-pad UDFN
Operating Voltage:
– 1.8 – 5.5V
Programming Voltage:
– 5V
Speed Grade
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
Industrial and Extended Temperature Ranges
Low Power Consumption
– Active Mode:
• 200µA at 1MHz and 1.8V
– Idle Mode:
• 25µA at 1MHz and 1.8V
– Power-down Mode:
• < 0.1µA at 1.8V
•
•
•
8-bit
Microcontroller
with 512/1024
Bytes In-System
Programmable
Flash
ATtiny4/5/9/10
•
•
•
•
•
•
Rev. 8127E–AVR–11/11
1. Pin Configurations
Figure 1-1.
Pinout of ATtiny4/5/9/10
SOT-23
(PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0
GND
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1
1
2
3
6
5
4
PB3 (RESET/PCINT3/ADC3)
VCC
PB2 (T0/CLKO/PCINT2/INT0/ADC2)
UDFN
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1
NC
NC
GND
1
2
3
4
8
7
6
5
PB2 (T0/CLKO/PCINT2/INT0/ADC2)
VCC
PB3 (RESET/PCINT3/ADC3)
PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0)
1.1
1.1.1
Pin Description
VCC
Supply voltage.
1.1.2
GND
Ground.
1.1.3
Port B (PB3..PB0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for
each bit. The output buffers have symmetrical drive characteristics, with both high sink and
source capability. As inputs, the port pins that are externally pulled low will source current if pull-
up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if
the clock is not running.
The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on
page 37.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-
imum pulse length is given in
Table 16-4 on page 120.
Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
2
ATtiny4/5/9/10
8127E–AVR–11/11
ATtiny4/5/9/10
2. Overview
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer
to optimize power consumption versus processing speed.
Figure 2-1.
Block Diagram
V
CC
RESET
PROGRAMMING
LOGIC
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
CALIBRATED
OSCILLATOR
PROGRAM
FLASH
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
INSTRUCTION
REGISTER
SRAM
RESET FLAG
REGISTER
INSTRUCTION
DECODER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
MCU
STATUS
REGISTER
CONTROL
LINES
TIMER/
COUNTER0
INTERRUPT
UNIT
ALU
ISP
INTERFACE
STATUS
REGISTER
8-BIT
DATA BUS
DATA REGISTER
PORT B
DIRECTION
REG. PORT B
ANALOG
COMPARATOR
ADC
DRIVERS
PORT B
PB3:0
GND
The AVR core combines a rich instruction set with 16 general purpose working registers and
system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock cycle.
The resulting architecture is compact and code efficient while achieving throughputs up to ten
times faster than conventional CISC microcontrollers.
3
8127E–AVR–11/11
The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable
Flash, 32 bytes of SRAM, four general purpose I/O lines, 16 general purpose working registers,
a 16-bit timer/counter with two PWM channels, internal and external interrupts, a programmable
watchdog timer with internal oscillator, an internal calibrated oscillator, and four software select-
able power saving modes. ATtiny5/10 are also equipped with a four-channel, 8-bit Analog to
Digital Converter (ADC).
Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), ana-
log comparator, and interrupt system to continue functioning. ADC Noise Reduction mode
minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules
except the ADC. In Power-down mode registers keep their contents and all chip functions are
disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running
while the rest of the device is sleeping, allowing very fast start-up combined with low power
consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-
chip, in-system programmable Flash allows program memory to be re-programmed in-system by
a conventional, non-volatile memory programmer.
The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools,
including macro assemblers and evaluation kits.
2.1
Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10
A comparison of the devices is shown in
Table 2-1.
Table 2-1.
Differences between ATtiny4, ATtiny5, ATtiny9 and ATtiny10
Flash
512 bytes
512 bytes
1024 bytes
1024 bytes
ADC
No
Yes
No
Yes
Signature
0x1E 0x8F 0x0A
0x1E 0x8F 0x09
0x1E 0x90 0x08
0x1E 0x90 0x03
Device
ATtiny4
ATtiny5
ATtiny9
ATtiny10
4
ATtiny4/5/9/10
8127E–AVR–11/11
ATtiny4/5/9/10
3. General Information
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
3.3
Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel
AVR microcontrollers. The QTouch Library includes support for QTouch
®
and QMatrix
®
acquisi-
tion methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the
Application Programming Interface (API) of the library to define the touch channels and sensors.
The application then calls the API to retrieve channel information and determine the state of the
touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more informa-
tion and details of implementation, refer to the QTouch Library User Guide – also available from
the Atmel website.
3.4
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
5
8127E–AVR–11/11
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