CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
d
t
V
SP
= V
SPO
= +5V, V
SM
= V
SMP
= -5V, GAIN = 2, T
A
= +25°C, exposed die plate = -5V, x2 = 5V,
R
LOAD
= 150Ω on all video outputs, unless otherwise specified.
DESCRIPTION
CONDITION
ISL59920
ISL59921
ISL59922
ISL59923
MIN
1.8
1.4
0.9
1.8
55
42.5
26.5
26.5
TYP MAX
2
1.5
1
2
62
2.2
1.7
1.2
2.3
68
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
Nominal Delay Increment (Note 2)
t
MAX
Maximum Delay
ISL59920
ISL59921
ISL59922
ISL59923
46.5 53.5
31
30
1
38.5
34.5
D
ELDT
t
PD
Delay Difference Between Channels for Same
Delay Settings On All Channels
Propagation Delay
ISL59920, ISL59923, measured input to
output, delay setting = 0ns
ISL59921, measured input to output, delay
setting = 0ns
ISL59922, measured input to output, delay
setting = 0ns
10
8
7
153
200
230
50
60
50
550
640
700
550
BW -3dB
3dB Bandwidth, 0ns Delay Time
ISL59920, ISL59923
ISL59921
ISL59922
BW ±0.1dB
±0.1dB Bandwidth, 0ns Delay Time
ISL59920, ISL59923
ISL59921
ISL59922
SR
Slew Rate
ISL59920, 20-80, delay = 0ns
ISL59921, 20-80, delay = 0ns
ISL59922, 20-80, delay = 0ns
ISL59923; 20-80, delay = 0ns
2
FN6826.2
August 31, 2010
ISL59920, ISL59921, ISL59922, ISL59923
Electrical Specifications
PARAMETER
t
R
- t
F
V
SP
= V
SPO
= +5V, V
SM
= V
SMP
= -5V, GAIN = 2, T
A
= +25°C, exposed die plate = -5V, x2 = 5V,
R
LOAD
= 150Ω on all video outputs, unless otherwise specified.
(Continued)
DESCRIPTION
Transient Response Time
CONDITION
ISL59920, 20% to 80%, for any delay, 1V step
delay = 0ns
ISL59921, 20% to 80%, for any delay, 1V step
delay = 0ns
ISL59922, 20% to 80%, for any delay, 1V step
delay = 0ns
ISL59923, 20% to 80%, for any delay, 1V step
delay = 0ns
V
OVER
Settling Time
THD
X
Voltage Overshoot
Output Settling after Delay Change / Offset
Calibration
Total Harmonic Distortion
Crosstalk
For any delay, response to 1V step input
Output settling time from rising edge of
SENABLE
1V
P-P
10MHz sinewave, offset by +0.2V at
mid delay setting
Stimulate G, measure R/B at 1MHz,
ISL59920, ISL59921, ISL59923
ISL59922
V
N
G_0
G_m
G_f
DG_m0
DG_f0
DG_fm
V
IN
Output Noise
Gain Zero Delay
Gain Mid Delay
Gain Full Delay
Difference in Gain, 0 to Mid
Difference in Gain, 0 to Full
Difference in Gain, Mid to Full
Input Voltage Range
ISL59920, Gain remains > 90% of nominal,
Gain = 2
ISL59921, Gain remains > 90% of nominal,
Gain = 2
ISL59922, Gain remains > 90% of nominal,
Gain = 2
ISL59923, Gain remains > 90% of nominal,
Gain = 2
I
B
R
IN
, G
IN
, B
IN
Input Bias Current
ISL59920, ISL59921
ISL59922, ISL59923
V
OS
Z
OUT
Output Offset Voltage
Output Impedance
Post offset calibration (Note 4), Delay = 0ns
and Delay = Full
ISL59920, ISL59921, Enabled,
Chip enable = 5V
ISL59922, ISL59923, Enabled,
Chip enable = 5V
Disabled, Chip enable = 0V
+PSRR
-PSRR
I
OUT
V
IH
V
IL
Rejection of Positive Supply
Rejection of Negative Supply
Output Drive Current
Logic High
Logic Low
10Ω load, 0.5V drive
Switch high threshold
Switch low threshold
0.8
43
Bandwidth = 150MHz
1.74
1.67
1.6
-8
-12
-10
-0.7
-0.7
-0.7
-0.7
3
1.5
-25
4.5
3.5
8
-42
-58
53
-29
-46
70
1.6
-4
5.4
6
MIN
TYP MAX
1.7
1.6
1.43
1.7
4
3
-43
-80
-78
2
1.8
1.8
1.8
0.6
-1.8
-1.7
1.92
1.97
2
7.5
10
7.5
1.1
1.04
1.04
1.15
8
8
+20
6.3
6.3
-38
-63
-59
UNIT
ns
ns
ns
ns
%
µs
dB
dB
dB
mV
RMS
V/V
V/V
V/V
%
%
%
V
V
V
V
µA
µA
mV
Ω
Ω
MΩ
dB
dB
mA
V
V
3
FN6826.2
August 31, 2010
ISL59920, ISL59921, ISL59922, ISL59923
Electrical Specifications
PARAMETER
V
SP
= V
SPO
= +5V, V
SM
= V
SMP
= -5V, GAIN = 2, T
A
= +25°C, exposed die plate = -5V, x2 = 5V,
R
LOAD
= 150Ω on all video outputs, unless otherwise specified.
(Continued)
DESCRIPTION
CONDITION
MIN
TYP MAX
UNIT
POWER SUPPLY CHARACTERISTICS
V+
V-
I
SP
V
SP
, V
SPO
Positive Supply Range
V
SM
, V
SMO
Negative Supply Range
Positive Supply Current (Note 3)
ISL59920
ISL59921, ISL59922
ISL59923
I
SPO
Positive Output Supply Current (Note 3)
ISL59920
ISL59921, ISL59922
ISL59923
I
SM
I
SMO
Negative Supply Current (Note 3)
Negative Output Supply Current (Note 3)
ISL59920, ISL59921, ISL59922
ISL59923
Δ
I
SP
+4.5
-4.5
98
98
74
11.3
11.3
9.9
-35.45
-15.5
-17.5
115
125
90
13
13
13
-31
-13
-13
0.9
2.6
+5.5
-5.5
127
146
106
15.3
16.3
16
-26
-11
-9.5
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply Current (Note 3)
Positive Supply Standby Current (Note 3)
Increase in I
SP
per unit step in delay per
channel
Chip enable = 0V
I
STANDBY
SERIAL INTERFACE CHARACTERISTICS
t
MAX
t
SEN_SETUP
Max SCLOCK Frequency
SENABLE to SCLOCK falling edge setup time.
See Figure 33.
Maximum programming clock speed
SENABLE falling edge should occur at least
t
SEN_SETUP
ns after previous (ignored) clock
and t
SEN_SETUP
before next (desired) clock.
Clock edges occurring within t_en_ck of the
SENABLE falling edge will have
indeterminate effect.
3
10
10
MHz
ns
t
SEN_CYCLE
Minimum Separation Between SENABLE rising
If SENABLE is taken low less than 3µs after it
edge and next SENABLE falling edge. See Figure 33. was taken high, there is a small possibility that
an offset correction will not be initiated.
µs
NOTES:
2. The limits for the “Nominal Delay Increment” are derived by taking the limits for the “Maximum Delay” and dividing by the number of steps for the
device. For the ISL59920, ISL59921, and ISL59922 the number of steps is 31; for the ISL59923 the number of steps is 15.
3. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
4. Offset measurements are referred to 75Ω load as shown in Figure 1.
75Ω
V
IN
x2
-
V
OUT
V
OS
75Ω
FIGURE 1. V
OS
MEASUREMENT CONDITIONS
4
FN6826.2
August 31, 2010
ISL59920, ISL59921, ISL59922, ISL59923
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Thermal Pad
PIN NAME
V
SP
R
IN
GND
G
IN
V
SM
B
IN
CENABLE
SENABLE
SDATA
SCLOCK
B
OUT
V
SMO
G
OUT
GNDO
R
OUT
V
SPO
TESTB
TESTG
TESTR
X2
PIN DESCRIPTION
+5V for delay circuitry and input amp
Red channel video input
0V for delay circuitry supply
Green channel video input
-5V for input amp
Blue channel video input
Chip Enable input, active high: logical high enables chip, low disables chip
Serial Enable input, active low: logical low enables serial communication
Serial Data input, logic threshold 1.2V: data to be programmed into chip
Serial Clock input: Clock to enter data; logical; data written on negative edge
Blue channel video output
-5V for video output buffers
Green channel video output
0V reference for input and output buffers
Red channel video output
+5V for video output buffers
Blue channel phase detector output
Green channel phase detector output
Red channel phase detector output
Gain Select Input: logical high = 2x (+6dB), logical low = 1x (0dB)
MUST be tied to -5V. For best thermal conductivity also tie to a larger -5V copper plane (inner
or bottom). Use many vias to minimize thermal resistance between thermal pad and copper
plane. Do not connect to GND - connection to GND is equivalent to shorting the -5V and GND
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