74HC32; 74HCT32
Quad 2-input OR gate
Rev. 7 — 30 September 2019
Product data sheet
1. General description
The 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
•
•
Complies with JEDEC standard JESD7A
Input levels:
•
For 74HC32: CMOS level
•
For 74HCT32: TTL level
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC32D
74HCT32D
74HC32DB
74HCT32DB
74HC32PW
74HCT32PW
74HC32BQ
74HCT32BQ
-40 °C to +125 °C
DHVQFN14
-40 °C to +125 °C
TSSOP14
-40 °C to +125 °C
SSOP14
-40 °C to +125 °C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Nexperia
74HC32; 74HCT32
Quad 2-input OR gate
4. Functional diagram
1
2
4
≥1
3
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
mna242
3
6
8
11
5
9
10
12
13
≥1
6
≥1
8
A
≥1
11
B
Y
mna241
mna243
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Logic diagram (one gate)
5. Pinning information
5.1. Pinning
terminal 1
index area
1B
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aad101
2
3
4
5
6
7
GND
14 V
CC
1
1A
13 4B
12 4A
14 V
CC
13 4B
12 4A
1Y
2A
2B
2Y
32
GND
(1)
8
11 4Y
10 3B
9
3A
32
11 4Y
10 3B
9
8
3A
3Y
3Y
001aad102
Transparent top view
Fig. 4.
Pin configuration SOT108-1 (SO14),
SOT337-1 (SSOP14) and SOT402-1 (TSSOP14)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5.
Pin configuration SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin
1, 4, 9, 12
2, 5, 10,13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
74HC_HCT32
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 7 — 30 September 2019
2 / 13
Nexperia
74HC32; 74HCT32
Quad 2-input OR gate
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
nA
L
L
H
H
nB
L
H
L
H
Output
nY
L
H
H
H
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
-0.5 V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
-0.5
-
-
-
-
-50
-65
[2]
-
Max
+7
±20
±20
±25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT108-1 (SO14) packages: P
tot
derates linearly with 10.1 mW/K above 100 °C.
For SOT337-1 (SSOP14) packages: P
tot
derates linearly with 7.3 mW/K above 81 °C.
For SOT402-1 (TSSOP14) packages: P
tot
derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) packages: P
tot
derates linearly with 9.6 mW/K above 98 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
-40
-
-
-
74HC32
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
-40
-
-
-
74HCT32
Typ
5.0
-
-
-
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
74HC_HCT32
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 7 — 30 September 2019
3 / 13
Nexperia
74HC32; 74HCT32
Quad 2-input OR gate
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC32
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
V
I
= V
IH
or V
IL
HIGH-level
output voltage
I
O
= -20 μA; V
CC
= 2.0 V
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -20 μA; V
CC
= 6.0 V
I
O
= -4.0 mA; V
CC
= 4.5 V
I
O
= -5.2 mA; V
CC
= 6.0 V
V
OL
V
I
= V
IH
or V
IL
LOW-level
output voltage
I
O
= 20 μA; V
CC
= 2.0 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
V
I
= V
CC
or GND; V
CC
= 6.0 V
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
2.0
4.5
6.0
4.32
5.81
0
0
0
0.15
0.16
-
-
3.5
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
±0.1
2.0
-
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1
20
-
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
40
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
μA
μA
pF
Conditions
Min
25 °C
Typ
Max
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
input
capacitance
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
74HCT32
V
IH
V
IL
V
OH
2.0
-
1.6
1.2
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
HIGH-level
output voltage
I
O
= -20 μA
I
O
= -4.0 mA
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
LOW-level
output voltage
I
O
= 20 μA
I
O
= 5.2 mA
4.4
3.98
-
-
4.5
4.32
0
0.15
-
-
0.1
0.25
4.4
3.84
-
-
-
-
0.1
0.33
4.4
3.7
-
-
-
-
0.1
0.4
V
V
V
V
V
OL
74HC_HCT32
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 7 — 30 September 2019
4 / 13
Nexperia
74HC32; 74HCT32
Quad 2-input OR gate
Conditions
Min
V
I
= V
CC
or GND; V
CC
= 5.5 V
-
-
-
25 °C
Typ
-
-
-
Max
±0.1
2.0
430
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
-
-
-
Max
±1
20
540
Min
-
-
-
Max
±1
40
590
μA
μA
μA
Symbol Parameter
I
I
I
CC
ΔI
CC
input leakage
current
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
additional
per input pin;
supply current V
I
= V
CC
- 2.1 V; I
O
= 0 A;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
input
capacitance
C
I
-
3.5
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for test circuit see
Fig. 7.
Symbol Parameter
Conditions
Min
74HC32
t
pd
propagation delay nA, nB to nY; see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
V
CC
= 6.0 V
t
t
transition time
see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power dissipation
capacitance
per package; V
I
= GND to V
CC
[3]
[2]
-
-
-
-
19
7
6
16
75
15
13
-
95
19
16
-
110
22
19
-
ns
ns
ns
pF
[1]
-
-
-
-
22
8
6
6
90
18
-
15
115
23
-
20
135
27
-
23
ns
ns
ns
ns
25 °C
Typ Max
-40 °C to
+85 °C
Max
-40 °C to Unit
+125 °C
Max
74HCT32
t
pd
propagation delay nA, nB to nY; see
Fig. 6
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
t
t
C
PD
[1]
[2]
[3]
[1]
-
-
[2]
[3]
-
-
11
9
7
28
24
-
15
-
30
-
19
-
36
-
22
-
ns
ns
ns
pF
transition time
power dissipation
capacitance
V
CC
= 4.5 V; see
Fig. 6
per package; V
I
= GND to V
CC
- 1.5 V
t
pd
is the same as t
PHL
and t
PLH
.
t
t
is the same as t
THL
and t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in μW):
2
2
P
D
= C
PD
× V
CC
× f
i
× N + Σ (C
L
× V
CC
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
2
Σ (C
L
× V
CC
× f
o
) = sum of outputs.
74HC_HCT32
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 7 — 30 September 2019
5 / 13
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