AT25DN256-XMHFGP-T datasheet, PDF

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AT25DN256-XMHFGP-T: Descriptionflash 256kb, 2.3V, 104mhz serial flash; Categorysemiconductor Other integrated circuit (IC); File Size2MB，38 Pages; ManufacturerAll Sensors; Environmental Compliance

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AT25DN256-XMHFGP-T Overview

flash 256kb, 2.3V, 104mhz serial flash

AT25DN256-XMHFGP-T Parametric

Parameter Name	Attribute value
Manufacture	Adesto Technologies
Product Category	Flash
RoHS	Yes
Data Bus Width	8 bi
Memory Type	Enhanced Serial Flash
Memory Size	256 kbi
Architecture	Flexible Erase
Timing Type	Synchronous
Interface Type	SPI
Access Time	-
Supply Voltage - Max	3.6 V
Supply Voltage - Mi	2.3 V
Maximum Operating Curre	12 mA
Operating Temperature	- 40 C to + 85 C
Mounting Style	SMD/SMT
Package / Case	TSSSOP-8
Packaging	Reel
Maximum Clock Frequency	104 MHz
Organizati	32 k x 8

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AT25DN256

256-Kbit, 2.3V Minimum

SPI Serial Flash Memory with Dual-Read Support

PRELIMINARY DATASHEET

Features



Single 2.3V - 3.6V Supply



Serial Peripheral Interface (SPI) Compatible

Supports SPI Modes 0 and 3

Supports Dual Output Read



104MHz Maximum Operating Frequency



Clock-to-Output (t

) of 6ns



Flexible, Optimized Erase Architecture for Code + Data Storage Applications



Uniform 256-Byte Page erase



Uniform 4-Kbyte Block Erase



Uniform 32-Kbyte Block Erase



Full Chip Erase



Hardware Controlled Locking of Protected Sectors via WP Pin



128-Byte Programmable OTP Security Register



Flexible Programming



Byte/Page Program (1 to 256 Bytes)



Fast Program and Erase Times



1.5ms Typical Page Program (256 Bytes) Time



40ms Typical 4-Kbyte Block Erase Time



320ms Typical 32-Kbyte Block Erase Time



Automatic Checking and Reporting of Erase/Program Failures



Software Controlled Reset



JEDEC Standard Manufacturer and Device ID Read Methodology



Low Power Dissipation



350nA Ultra Deep Power Down current (Typical)

5µA Deep Power-Down Current (Typical)

25uA Standby current (Typical)

6mA Active Read Current (Typical)



Endurance: 100,000 Program/Erase Cycles



Data Retention: 20 Years



Complies with Full Industrial Temperature Range



Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options



8-lead SOIC (150-mil)

8-pad Ultra Thin DFN (2 x 3 x 0.6mm)

8-lead TSSOP Package

DS-25DN256–039B–5/2014

Description

The Adesto

AT25DN256 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer

based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The

flexible erase architecture of the AT25DN256, with its page erase granularity it is ideal for data storage as well, eliminating the

need for additional data storage devices.

The erase block sizes of the AT25DN256 have been optimized to meet the needs of today's code and data storage applications.

By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules

and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that

occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space

efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device

density.

The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as

unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.

Specifically designed for use in many different systems, the AT25DN256 supports read, program, and erase operations with a

wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming and erasing.

Pin Descriptions and Pinouts

Pin Descriptions

Asserted

State

Table 2-1.

Symbol

Name and Function

CHIP SELECT:

Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),

and the SO pin will be in a high-impedance state. When the device is deselected, data will not be

accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition

is required to end an operation. When ending an internally self-timed operation such as a program

or erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always

latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the

falling edge of SCK.

SERIAL INPUT:

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched in on the rising

edge of SCK.

Type

Low

Input

SCK

Input

SI (I/O

)

With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O

) in conjunction with

other pins to allow two bits of data on (I/O

1-0

) to be clocked out on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the SI (I/O

) pin will be referenced as the SI

pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O

Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).

SERIAL OUTPUT:

The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK.

Input/

Output

(I/O

)

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O

) in conjunction with

other pins to allow two bits of data on (I/O

1-0

) to be clocked out on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the SO (I/O

) pin will be referenced as the SO

pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O

The SO pin will be in a high-impedance state whenever the device is deselected (CS is

deasserted).

Input/

Output

AT25DN256

DS-25DN256–039B–5/2014

AT25DN256-XMHFGP-T Related Products

	AT25DN256-XMHFGP-T	AT25DN256-SSHFGP-B	AT25DN256-XMHFGP-B	AT25DN256-SSHFGP-T	AT25DN256-MAHFGP-T
Description	flash 256kb, 2.3V, 104mhz serial flash	flash 256kb, 2.3V, 104mhz serial flash	flash 256kb, 2.3V, 104mhz serial flash	flash 256kb, 2.3V, 104mhz serial flash	flash 256kb, 2.3V, 104mhz serial flash
Manufacture	Adesto Technologies	Adesto Technologies	Adesto Technologies	Adesto Technologies	Adesto Technologies
Product Category	Flash	Flash	Flash	Flash	Flash
RoHS	Yes	Yes	Yes	Yes	Yes
Data Bus Width	8 bi	8 bi	8 bi	8 bi	8 bi
Memory Type	Enhanced Serial Flash	Enhanced Serial Flash	Enhanced Serial Flash	Enhanced Serial Flash	Enhanced Serial Flash
Memory Size	256 kbi	256 kbi	256 kbi	256 kbi	256 kbi
Architecture	Flexible Erase	Flexible Erase	Flexible Erase	Flexible Erase	Flexible Erase
Timing Type	Synchronous	Synchronous	Synchronous	Synchronous	Synchronous
Interface Type	SPI	SPI	SPI	SPI	SPI
Supply Voltage - Max	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Supply Voltage - Mi	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Maximum Operating Curre	12 mA	12 mA	12 mA	12 mA	12 mA
Operating Temperature	- 40 C to + 85 C	- 40 C to + 85 C	- 40 C to + 85 C	- 40 C to + 85 C	- 40 C to + 85 C
Mounting Style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
Package / Case	TSSSOP-8	SOIC-8 Narrow	TSSSOP-8	SOIC-8 Narrow	UDFN-8
Packaging	Reel	Tube	Tube	Reel	Reel
Maximum Clock Frequency	104 MHz	104 MHz	104 MHz	104 MHz	104 MHz
Organizati	32 k x 8	32 k x 8	32 k x 8	32 k x 8	32 k x 8

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