STA304A
DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™
PRODUCT PREVIEW
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STA304AEND TO END DIGITAL AUDIO
INTEGRATED SOLUTION
· DSP Functions:
- DIGITAL VOLUME CONTROL
- SOFT MUTE
- BASS and TREBLE
- PARAMETRIC EQ PER CHANNEL
- BASS MANAGEMENT FOR SUBWOOFER
- AUTO MUTE ON ZERO INPUT DETECTION
4+1 DIRECT DIGITAL AMPLIFICATION
(DDX™) OUTPUT CHANNELs
6 CHANNELs PROGRAMMABLE SERIAL
OUTPUT INTERFACE (by default I2S)
4 CHANNELs PROGRAMMABLE SERIAL
INPUT INTERFACE (by default I2S)
STEREO S/PDIF INPUT INTERFACE
Intel AC'97 LINK (rev. 2.1) INPUT INTERFACE
FOR AUDIO AND CONTROL
ON CHIP AUTOMATIC INPUT SAMPLING
FREQUENCY DETECTION
100 dB SNR SAMPLE RATE CONVERTER
(1KHz SINUSOIDAL INPUT)
I
2
C CONTROL BUS
LOW POWER 3.3V CMOS TECHNOLOGY
TQFP44
ORDERING NUMBER: STA304A
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EMBEDDED PLL FOR INTERNAL CLOCK
GENERATION (1024x48 kHz = 49.152 MHz)
6.144 MHz EXTERNAL INPUT CLOCK OR
BUILT-IN INDUSTRY STANDARD XTAL
OSCILLATOR
VARIABLE DIGITAL GAIN UP TO 24dB
(0.75dB STEP)
1.0 DESCRIPTION
The STA304A Digital Audio Processor is a single
chip device implementing end to end digital solution
for audio application. In conjunction with STA500
power bridge it gives the full digital DSP-to-power
high quality chain with no need for audio Digital-to-
Analog converters between DSP and power stage.
s
s
BLOCK DIAGRAM
SA
11
SCL
10
SDA
9
LRCKI / SYNC
BICKI / BIT_CL
3
4
29
LEFT_A
LEFT_B
RIGHT_A
RIGHT_B
SLEFT_A
SLEFT_B
SRIGHT_A
SRIGHT_B
LFE_A
LFE_B
I2C
I2S
ROM
DDX
30
27
28
33
34
23
SDI_1 / SDATA_OUT 1
SDI_2 / SDATA_IN 2
RXP
RXN
24
18
19
S/PDIF
SRC
DSP
21
22
43
43
LRCKO
BICKO
I2S
43
SDO_1
SDO_2
SDO_3
RAM
AC`97
43
43
RESET
7
PLL
PowerDown
35
EAPD
14
XTI
15
XTO
43
CKOUT
44
PWDN
March 2002
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/30
STA304A
1.0 DESCRIPTION
(continued)
The device supports two main configurations as far as input sources: AC'97 input or IIS/SPDIF input: selection
is made via a dedicated pin (AC97_MODE pin). The AC`97 can be configured to work in two different ways:
'Full Compliant' mode and 'Proprietary' mode which enables more features. The selection of the operating mode
is done via a specific bit in a Vendor Reserved register (see bit 0: AC97_FC_mode in the CRA register, address
5Ah).
The 'Full Compliant' mode is compliant with rev. 2.1 of AC`97 link specifications.
This link can provide up to 6 input audio channels with sampling frequency of 44.1, 48, 88.2, 96 kHz, and the
related controls.
In the IIS/SPDIF mode, a stereo S/PDIF and a 4 channels three-wires programmable serial input interface work
in mutually exclusive way. Two channels with sampling frequency in the continuous range from 32 to 96 kHz
are supported by the S/PDIF interface. Up to four channels with sampling frequency varying continuously from
32kHz up to 96 kHz are supported by the programmable serial interfaces. Among the different configurations,
also the standard IIS protocol is supported.
An embedded high quality sample rate converter (SRC) resamples input data at the internal fixed sampling fre-
quency of 48 kHz for DSP operations.
The DSP is a 20x20 bit core audio processor performing several user controlled parametric algorithms, among
them are dynamic and static equalization, Bass, Treble, Volume control and more. The DSP operates at
49.152MHz (1024xfs). This frequency is generated by an internal PLL with programmable multiplication factor
(x2 or x8).
This device has 5 channels Direct Digital Amplification (DDX™ technology), performing high efficiency class-D
PWM output signals used to drive directly external power bridge stages (STA500).
In addition a 6 channel digital output programmable interface (supporting IIS standard protocol) is embedded
for applications with commercial audio D/A converters. The output sampling frequency is fixed at 48 kHz when
the interface operates as master. In addition an oversampled clock (256xfs or 512xfs) is provided externally for
the D/A converters.
An IIC interface allows full programmability of internal algorithms and control registers via an external controller.
An arbitration logic handles access conflicts to embedded control registers (which may occur as a consequence
of contemporary access to control registers by AClink, IIC and DSP blocks).
Figure 1. DSP data processing
SL/SR/LFE
BASS
REDIR
CNT
L/R
L,R,SL,SR,LFE,CNT
STATIC &
DINAMIC
EQ
L/R
L,R,SL,SR,LFE
VOLUME
I2S +
DDX
CENTER
VOLUME
PHANTOM
CENTER
L/R
BASS
TREBLE
CNT
I2S
D01AU1310
2/30
STA304A
PIN CONNECTION
(Top view)
CKOUT
LRCKO
GND_5
SDO_3
SDO_2
SDO_1
VDD_5
PWDN
SCKO
EAPD
35
44
43
42
41
40
39
38
37
36
SLEFT_A
34
33
32
31
30
29
28
27
26
25
24
23
SDI_1/SDATA_OUT
SDI_2/SDATA_IN
LRCKI/SYNC
BICKI/BIT_CLK
VDD_1
GND_1
RESET
AC97_MODE
SDA
SCL
SA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SLEFT_B
VDD_4
GND_4
LEFT_A
LEFT_B
RIGHT_A
RIGHT_B
VDD_3
GND_3
SRIGHT_A
SRIGHT_B
TEST_MODE
VDD_2
XTI
XTO
GND_2
VCC
RXP
RXN
VSS
LFE_B
LFE_A
D00AU1160
PIN FUNCTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
SDI_1 / SDATA_OUT
SDI_2 / SDATA_IN
LRCKI / SYNC
BICKI / BIT_CLK
VDD_1
GND_1
RESET
AC97_MODE
SDA
SCL
SA
TEST_MODE
VDD_2
XTI
XTO
GND_2
I
O
I
I
I
I/O
I
TYPE
I
I/O
I/O
I/O
DESCRIPTION
Input I2S Serial Data 1 / AC97 Output Data
Input I2S Serial Data 2 / AC97 Input Data
Input I2S Left/Right Clock / AC97 Synch.
Clock
Input I2S Serial Clock / AC97 Bit Clock
Digital Supply Voltage
Digital Ground
Global Reset
(This pin is sensed only after 2 clock cycles)
AC97 Enable / Disable (1=AC97; 0=I2S/
SPDIF)
I2C Serial Data
I2C Serial Clock
Select Address (I2C / AC97)
Test Mode (Active High)
Digital Supply Voltage
Crystal Input (Clock input)
Crystal Output
Digital Ground
Analog IN
CMOS Out Oscill. Pad
CMOS Schmitt In Pull-Up
CMOS Schmitt In Pull-Down
CMOS In / CMOS Out 2mA
CMOS In
CMOS In
CMOS
PAD TYPE
CMOS Schmitt In
CMOS In / CMOS Out 2mA
CMOS In / CMOS Out 2mA
CMOS In / CMOS Out 4mA
3/30
STA304A
PIN FUNCTION
(continued)
PIN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NAME
VCC
RXP
RXN
VSS
LFE_B
LFE_A
SRIGHT_B
SRIGHT_A
GND_3
VDD_3
RIGHT_B
RIGHT_A
LEFT_B
LEFT_A
GND_4
VDD_4
SLEFT_B
SLEFT_A
EAPD
LRCKO
SDO_1
SDO_2
SDO_3
SCKO
GND_5
VDD_5
CKOUT
PWDN
O
I
O
O
O
I/O
O
O
O
I/O
O
O
O
O
O
O
O
O
I
I
TYPE
DESCRIPTION
Analog Supply Voltage
S/PDIF receiver positive
S/PDIF receiver negative
Analog Ground
Pwm LFE (subwoofer) output channel (B)
Pwm LFE (subwoofer) output channel (A)
Pwm Surround Right output channel (B)
Pwm Surround Right output channel (A)
Digital Ground
Digital Supply Voltage
Pwm Right output channel (B)
Pwm Right output channel (A)
Pwm Left output channel (B)
Pwm Left output channel (A)
Digital Ground
Digital Supply Voltage
Pwm Surround Left output channel (B)
Pwm Surround Left output channel (A)
External Amplifier Powerdown (Active Low)
Output I2S Left/Right Clock
Output I2S Serial Data 1
Output I2S Serial Data 2
Output I2S Serial Data 3
Output I2S Serial Clock
Digital Ground
Digital Supply Voltage
Clock Output (12 /24 MHz)
Device Powerdown (Active Low)
CMOS Out 8mA
CMOS In Pull-Up
CMOS Out 3mA
CMOS Out 3mA
CMOS Out 2mA
CMOS In / CMOS Out 2mA
CMOS Out 2mA
CMOS Out 2mA
CMOS Out 2mA
CMOS In / CMOS Out 4mA
CMOS Out 3mA
CMOS Out 3mA
CMOS Out 3mA
CMOS Out 3mA
CMOS Out 3mA
CMOS Out 3mA
CMOS Out 3mA
CMOS Out 3mA
Analog In
Analog In
PAD TYPE
4/30
STA304A
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
i
V
o
T
stg
T
op
P
DD
P
DA
Power Supply
Voltage on input pins
Voltage on output pins
Storage Temperature
Operative ambient temperature
Power Consumption Digital
Power Consumption Analog
Parameter
Value
-0.3 to 4
-0.3 to VDD+0.3
-0.3 to VDD+0.3
-40 to +150
-20 to +85
tbd
tbd
Unit
V
V
V
°C
°C
mW
mW
THERMAL DATA
Symbol
R
thj-amb
Parameter
Thermal resistance Junction to Ambient
Value
85
Unit
°C/W
ELECTRICAL CHARACTERISTCS
(V
DD
= 3.3V ± 0.3V; T
amb
= 0 to 70 °C; unless otherwise specified)
DC OPERATING CONDITIONS
Symbol
V
DD
T
j
Power Supply Voltage
Operating Junction Temperature
Parameter
Value
3.0 to 3.6V
-20 to 125
°C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
I
il
I
ih
V
esd
Parameter
Low Level Input Current Without
pull-up device
High Level Input Current
Without pull-up device
Electrostatic Protection
Test Condition
V
i
= 0V
V
i
= V
DD
= 3.6V
Leakage < 1µA
Min.
-10
-10
2000
Typ.
Max.
10
10
Unit
µA
µA
V
Note
1
1
2
Note 1: The leakage currents are generally very small, < 1na. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model
5/30
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