MSM7578HRS datasheet, PDF - EEWORLD Datasheet

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MSM7578HRS: DescriptionSingle Rail CODEC; CategoryWireless rf/communication Telecom circuit; File Size149KB，18 Pages; ManufacturerOKI; Websitehttp://www.oki.com

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MSM7578HRS Overview

Single Rail CODEC

MSM7578HRS Parametric

Parameter Name	Attribute value
Maker	OKI
Parts packaging code	DIP
package instruction	DIP,
Contacts	16
Reach Compliance Code	unknow
Law of compression and extension	MU-LAW
filter	YES
JESD-30 code	R-PDIP-T16
length	19.05 mm
Number of functions	1
Number of terminals	16
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
Maximum seat height	5.08 mm
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Telecom integrated circuit types	PCM CODEC
Temperature level	OTHER
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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E2U0017-28-81

¡ Semiconductor

MSM7578H/7578V/7579

¡ Semiconductor

Single Rail CODEC

This version: Aug. 1998

MSM7578H/7578V/7579

Previous version: Nov. 1996

GENERAL DESCRIPTION

The MSM7578 and MSM7579 are single-channel CODEC CMOS ICs for voice signals ranging

from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.

Designed especially for a single-power supply and low-power applications, these devices are

particularly optimized for telephone terminals in digital wireless systems and ISDN systems.

The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.

The analog output signal can directly drive a piezoelectric type handset receiver.

FEATURES

• Single power supply: +5.0 V

±5%

• Low power consumption

Operating mode:

25 mW Typ. 47 mW Max. V

= 5 V

Power down mode:

0.05 mW Typ. 0.3 mW Max. V

= 5 V

• ITU-T Companding law

MSM7578H:

m-law

MSM7579:

A-law

MSM7578V:

m/A-law

pin-selectable

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

• Adjustable transmit gain

• Built-in reference voltage supply

• Directly drive a line transformer of 600

• The 16-pin DIP and 24-pin SOP package products provide pin compatibility with the MSM7508B/

7509B

• The 20-pin SSOP package products have 1/3 the foot print of conventional products

• Package options:

16-pin plastic DIP (DIP16-P-300-2.54)

(Product name : MSM7578HRS)

(Product name : MSM7579RS)

(Product name : MSM7578VRS)

24-pin plastic SOP (SOP24-P-430-1.27-K)

(Product name : MSM7578HGS-K)

(Product name : MSM7578VGS-K)

(Product name : MSM7579GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7578HMS-K)

(Product name : MSM7579MS-K)

(Product name : MSM7578VMS-K)

1/18

¡ Semiconductor

Power supply for +5 V.

PCMIN

MSM7578H/7578V/7579

PCM signal input.

A serial PCM signal input to this pin is converted to an analog signal in synchronization with the

RSYNC signal and BCLK signal.

The data rate of the PCM signal is equal to the frequency of the BCLK signal.

The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register

when shifted by eight bits.

The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.

The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,

or 200 kHz. Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the

power saving state.

RSYNC

Receive synchronizing signal input.

Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive

synchronizing signal.

Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLK. The frequency should be 8 kHz

±50

ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.

However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz

±2

kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.

The PCM output signal from the PCMOUT pin is output in synchronization with this transmit

synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing

signals of the transmit section.

This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz

±50

ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.

However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz

±2

kHz, but the electrical characteristics in this specification are

not guaranteed.

Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the power saving

state.

5/18

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