EEWORLDEEWORLDEEWORLD

Part Number

Search

ZPLK-20-659SN

Description
Circular Connector, 7 Contact(s), Aluminum Alloy, Female, Crimp Terminal, Plug,
CategoryThe connector    The connector   
File Size103KB,1 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Download Datasheet Parametric View All

ZPLK-20-659SN Overview

Circular Connector, 7 Contact(s), Aluminum Alloy, Female, Crimp Terminal, Plug,

ZPLK-20-659SN Parametric

Parameter NameAttribute value
Objectid1446597873
Reach Compliance Codeunknown
YTEOL8.47
Other featuresLOW PROFILE
Back shell typeSOLID
Body/casing typePLUG
Connector typeCIRCULAR CONNECTOR
Contact point genderFEMALE
Coupling typeSNAP
DIN complianceNO
empty shellNO
Environmental characteristicsCORROSION RESISTANT
Filter functionNO
IEC complianceNO
MIL complianceNO
Plug informationMULTIPLE MATING PARTS AVAILABLE
Mixed contactsNO
Installation typeCABLE
OptionsGENERAL PURPOSE
Shell surfaceANODIC
Shell materialALUMINUM ALLOY
Housing size20
Termination typeCRIMP
Total number of contacts7
Help with the modulation method implementation of RFID based on software radio
[align=left][font=宋体][color=rgb(0, 0, 0)][size=10.5pt][b][Main content][/b][/size][/color][/font]Understand the modulation method of RFID, the working principle and usage of GNU Radio USRP open source...
runhard RF/Wirelessly
How to remove "not signed in" on the title in altium designer crack
After dxp is cracked, the following pattern appears on the title. How can I remove "not signed in"?...
jerome201314 PCB Design
The seven-segment digital tube is not bright enough
I have encountered a problem in my graduation project. When I display the year, month, day, hour, minute and second, if I add a delay subroutine to the display program, the LED digital tube will be br...
csfcsf Embedded System
Please recommend a power management chip
Could anyone please recommend a power management chip?...
lingwang Power technology
FPGA cannot detect the data sent on the bus
Line 4 in the waveform is wr, and the chip select signal is always low. Lines 15/14/13/12 are datain【0】, datain【1】, datain【2】, and datain【3】, respectively. Datain【0】 is always high, datain【1】 is alway...
whllieying FPGA/CPLD
The output of the peak detection circuit is not the peak value of the input signal. The peak value of the input signal is 25mv-2.5V and the maximum frequency is 1Mhz
Why is the output of the peak detection circuit not the peak value of the input signal? I changed the input signal peak value to the range of 25mv-2.5V and the maximum frequency to 1Mhz. Sometimes the...
wuli1314 Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 301  1871  2544  277  2615  7  38  52  6  53 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号