EEWORLDEEWORLDEEWORLD

Part Number

Search

320-6.144M-5FN-TNCG-TR

Description
HCMOS/TTL Output Clock Oscillator, 6.144MHz Nom, GULLWING, DIP-8/4
CategoryPassive components    oscillator   
File Size138KB,3 Pages
ManufacturerOscilent
Websitehttp://www.oscilent.com
Environmental Compliance  
Download Datasheet Parametric View All

320-6.144M-5FN-TNCG-TR Overview

HCMOS/TTL Output Clock Oscillator, 6.144MHz Nom, GULLWING, DIP-8/4

320-6.144M-5FN-TNCG-TR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid1360484958
Reach Compliance Codecompliant
Other featuresTR
maximum descent time10 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
Installation featuresSURFACE MOUNT
Number of terminals8
Nominal operating frequency6.144 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeHCMOS/TTL
longest rise time10 ns
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
maximum symmetry55/45 %
Oscilent Corporation | 320 Series Crystal Oscillator
Page 1 of 3
Crystal Oscillator
Series Number
Package
Description
Last Modified
320
FEATURES
- HCMOS/TTL logic compatible
- Wide frequency range
- Low power consumption
- Industry standard package
- 5V or 3.3V optional
- RoHs / Lead Free compliant
Metal Dip Half Size
Clock Oscillators
July 01 2005
OPERATING CONDITIONS / ELECTRICAL CHARACTERISTICS
PARAMETERS
Output Logic
Input Voltage (VDD)
Frequency Range (f
O
)
Operating Temperature (T
OPR
)
Storage Temperature (T
STG
)
Overall Frequency Stability
CONDITIONS
-
-
-
-
-
a+b+c+d
(a) Frequency Tolerance
(b) Temperature Stability
(c) Input Voltage Stability
(d) Load Stability
Input Current (I
DD
)
Aging
Rise Time (T
R
) / Fall Time (T
F
)
Rise Time (T
R
) / Fall Time (T
F
)
Output Voltage High "1" VOH
Output Voltage Low "0" VOL
Duty Cycle
Start-Up Time (T
S
)
Jitter
-
@ 25°C
< 66.660 MHz
66.660 MHz
TTL Load
HCMOS Load
TTL Load
HCMOS Load
-
-
(One Sigma)
2.7 min.
0.4 max.
0.5 max.
50 ±10 (Std.) / 50 ±5 (Option)
10 max.
±25 max.
CHARACTERISTICS
HCMOS / TTL Output
3.3 ±10%
0.50 ~ 125.000
5.0 ±10%
0.50 ~ 125.000
UNITS
-
VDC
MHz
°C
°C
PPM
-
-
-
-
mA
PPM/Y
nS
nS
VDC
VDC
%
ms
ps
0 ~ +70 (Std.) / -40 ~ 85 (Option)
-55 ~ +125
±20, ±25, ±50, ±100 max.
Inclusive of Overall Stability
Inclusive of Overall Stability (Operating Temperature)
Inclusive of Overall Stability (VDD ±5%)
Inclusive of Overall Stability (RL ±5%)
10 ~ 45 max.
±5 max.
10 max. (0.4V to 2.4V w/ TTL, Waveform / HCMOS)
4 max. (0.4V to 2.4V w/ TTL, Waveform / HCMOS)
2.4 min.
VDD-0.5 min.
15 ~ 85 max.
PIN CONNECTIONS
#1
No Connection or Tri-State
Credit Suisse report: Russia's wealth gap is the largest in the world, and Chinese family wealth continues to grow
On the 9th, the Swiss-based Credit Suisse Research Institute released its fourth annual Global Wealth Report. The report said that since 2000, China's per capita wealth has almost quadrupled, from $5,...
walkwk Talking
Do I need to solder the capacitor next to the external 32768 crystal oscillator of MSP-EXP430G2?
When I was learning about the MSP-EXP430G2 board, TI gave me a 32768 crystal oscillator. I wanted to solder it on, but I saw that there were positions for two 12pf capacitors on the circuit, but TI di...
lkl0305 Microcontroller MCU
Why is the triangle wave sampled by my AD like this? It doesn't specify what the unit of the vertical axis is.
Why is the triangle wave sampled by my AD like this? It doesn't specify what the unit of the vertical axis is....
双子charming1 DSP and ARM Processors
Key points of transformer design
Key points of transformer design (1) Both the pulse source and the load are field effect tubes, and their input capacitance is relatively large. Usually, the magnetic reset is accelerated by reducing ...
zbz0529 Power technology
PCB LAYOUT Technology Encyclopedia
1. Common errors in schematics: (1) ERC reports that the pin is not connected to the signal: a. The I/O attribute is defined for the pin when creating the package; b. The inconsistent grid attribute i...
kandy2059 PCB Design
FPGA controls DSP power-on reset procedure
module DSP_RST(input clk_25m,input RESETSTAT, //DSP reset status 0 means reset status 1 means working statusinput LOCKED, //Is the clock module normal?output ref LRESETNMIENz = 1'b0,//局部复位管脚output reg...
Jacktang DSP and ARM Processors

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 656  1024  395  1371  397  14  21  8  28  36 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号