EEWORLDEEWORLDEEWORLD

Part Number

Search

320-7.3728M-3F-TTSG-TR

Description
HCMOS/TTL Output Clock Oscillator, 7.3728MHz Nom, GULLWING, DIP-8/4
CategoryPassive components    oscillator   
File Size138KB,3 Pages
ManufacturerOscilent
Websitehttp://www.oscilent.com
Environmental Compliance  
Download Datasheet Parametric View All

320-7.3728M-3F-TTSG-TR Overview

HCMOS/TTL Output Clock Oscillator, 7.3728MHz Nom, GULLWING, DIP-8/4

320-7.3728M-3F-TTSG-TR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid1360485846
Reach Compliance Codecompliant
Other featuresTRI-STATE; ENABLE/DISABLE FUNCTION; TR
maximum descent time10 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
Installation featuresSURFACE MOUNT
Number of terminals8
Nominal operating frequency7.3728 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typeHCMOS/TTL
longest rise time10 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Oscilent Corporation | 320 Series Crystal Oscillator
Page 1 of 3
Crystal Oscillator
Series Number
Package
Description
Last Modified
320
FEATURES
- HCMOS/TTL logic compatible
- Wide frequency range
- Low power consumption
- Industry standard package
- 5V or 3.3V optional
- RoHs / Lead Free compliant
Metal Dip Half Size
Clock Oscillators
July 01 2005
OPERATING CONDITIONS / ELECTRICAL CHARACTERISTICS
PARAMETERS
Output Logic
Input Voltage (VDD)
Frequency Range (f
O
)
Operating Temperature (T
OPR
)
Storage Temperature (T
STG
)
Overall Frequency Stability
CONDITIONS
-
-
-
-
-
a+b+c+d
(a) Frequency Tolerance
(b) Temperature Stability
(c) Input Voltage Stability
(d) Load Stability
Input Current (I
DD
)
Aging
Rise Time (T
R
) / Fall Time (T
F
)
Rise Time (T
R
) / Fall Time (T
F
)
Output Voltage High "1" VOH
Output Voltage Low "0" VOL
Duty Cycle
Start-Up Time (T
S
)
Jitter
-
@ 25°C
< 66.660 MHz
66.660 MHz
TTL Load
HCMOS Load
TTL Load
HCMOS Load
-
-
(One Sigma)
2.7 min.
0.4 max.
0.5 max.
50 ±10 (Std.) / 50 ±5 (Option)
10 max.
±25 max.
CHARACTERISTICS
HCMOS / TTL Output
3.3 ±10%
0.50 ~ 125.000
5.0 ±10%
0.50 ~ 125.000
UNITS
-
VDC
MHz
°C
°C
PPM
-
-
-
-
mA
PPM/Y
nS
nS
VDC
VDC
%
ms
ps
0 ~ +70 (Std.) / -40 ~ 85 (Option)
-55 ~ +125
±20, ±25, ±50, ±100 max.
Inclusive of Overall Stability
Inclusive of Overall Stability (Operating Temperature)
Inclusive of Overall Stability (VDD ±5%)
Inclusive of Overall Stability (RL ±5%)
10 ~ 45 max.
±5 max.
10 max. (0.4V to 2.4V w/ TTL, Waveform / HCMOS)
4 max. (0.4V to 2.4V w/ TTL, Waveform / HCMOS)
2.4 min.
VDD-0.5 min.
15 ~ 85 max.
PIN CONNECTIONS
#1
No Connection or Tri-State
"Design and Application Examples of Single Chip Microcomputer Fuzzy Control System"
The knowledge in "Design and Application Examples of Single-Chip Microcomputer Fuzzy Control Systems" will never expire... Come on, let's make progress together!...
cuizhihao MCU
Computer failure
Hello everyone! Please give me some advice! After I reinstalled the system on my computer, I don't know why there is no sound after the installation. The USB keyboard and mouse I bought don't work whe...
msucl Embedded System
/The RTC time displayed by gui overlaps, and the next time ARM displays the result, it will overwrite the last displayed result.
Everything is normal, the compilation in ADS can pass, and the surface can be simulated in AXD. The program is a cut from a tested normal program. Problem: For example, when second shows 20 at point (...
87136226 ARM Technology
Do you want to improve your development skills? Do you want your salary to increase?
We set up this studio to provide a learning and entrepreneurial platform for embedded system software and hardware engineers. For those who want to learn embedded system software and hardware developm...
fys5627300 Embedded System
Ask about the pin setting before Altera FPGA configuration
When setting the FPGA's IO pins in the Pin Planner window of the Quartus II environment, what do "I/O Standard", "Reseved", "Current Strength" and "VREF Group" mean? How can I set them appropriately? ...
fangliball FPGA/CPLD
How to implement data exchange between two user-mode applications through a driver?
The serial port application (user mode) calls the virtual serial port and sends data to the virtual serial port. The service program (user mode) packages the data to be sent by the virtual serial port...
fgfz2003 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2846  1012  1535  1133  532  58  21  31  23  11 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号