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UPA2714GR

Description
Small Signal Field-Effect Transistor, 7A I(D), 30V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8
CategoryDiscrete semiconductor    The transistor   
File Size91KB,8 Pages
ManufacturerNEC Electronics
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UPA2714GR Overview

Small Signal Field-Effect Transistor, 7A I(D), 30V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, SOP-8

UPA2714GR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codecompli
ECCN codeEAR99
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage30 V
Maximum drain current (ID)7 A
Maximum drain-source on-resistance0.034 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
JESD-609 codee0
Number of components1
Number of terminals8
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeP-CHANNEL
Certification statusNot Qualified
surface mountYES
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA2714GR
SWITCHING
P-CHANNEL POWER MOS FET
DESCRIPTION
The
µ
PA2714GR is P-Channel MOS Field Effect Transistor
designed for power management applications of notebook
computers and Li-ion battery protection circuit.
PACKAGE DRAWING (Unit: mm)
8
5
1, 2, 3
; Source
4
; Gate
5, 6, 7, 8 ; Drain
1.8 MAX.
Low on-state resistance
R
DS(on)1
= 20 mΩ MAX. (V
GS
=
10 V, I
D
=
3.5 A)
R
DS(on)2
= 30 mΩ MAX. (V
GS
=
4.5 V, I
D
=
3.5 A)
R
DS(on)3
= 34 mΩ MAX. (V
GS
=
4.0 V, I
D
=
3.5 A)
Low C
iss
: C
iss
= 1370 pF TYP.
Small and surface mount package (Power SOP8)
FEATURES
1
4
5.37 MAX.
+0.10
–0.05
6.0 ±0.3
4.4
0.8
1.44
0.15
0.05 MIN.
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
µ
PA2714GR
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
Note3
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T1
P
T2
T
ch
T
stg
30
V
V
A
A
W
W
°C
°C
A
mJ
Source
Gate
Drain
m20
m7
m28
2
2
150
55 to +150
7
EQUIVALENT CIRCUIT
Total Power Dissipation
Total Power Dissipation
Channel Temperature
Storage Temperature
Body
Diode
Single Avalanche Current
Single Avalanche Energy
Notes 1.
2.
3.
4.
Remark
Note4
Note4
I
AS
E
AS
4.9
PW
10
µ
s, Duty Cycle
1%
2
Mounted on a ceramic substrate of 1200 mm x 2.2 mm
Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm) , PW = 10 sec
Starting T
ch
= 25°C, V
DD
=
15 V, R
G
= 25
Ω,
L = 100
µ
H, V
GS
=
20
0 V
Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,
and quickly dissipate it once, when it has occurred.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
Document No.
G15982EJ2V0DS00 (2nd edition)
Date Published November 2002 NS CP(K)
Printed in Japan
The mark
!
shows major revised points.
2002
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