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UPA1814GR-9JG

Description
Small Signal Field-Effect Transistor, 7A I(D), 30V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, TSSOP-8
CategoryDiscrete semiconductor    The transistor   
File Size69KB,8 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPA1814GR-9JG Overview

Small Signal Field-Effect Transistor, 7A I(D), 30V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, POWER, TSSOP-8

UPA1814GR-9JG Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeTSSOP
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codecompli
ECCN codeEAR99
Other featuresESD PROTECTED
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage30 V
Maximum drain current (ID)7 A
Maximum drain-source on-resistance0.027 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
JESD-609 codee0
Number of components1
Number of terminals8
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeP-CHANNEL
Certification statusNot Qualified
surface mountYES
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1814
P-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
DESCRIPTION
The
µ
PA1814 is a switching device which can be
driven directly by a 4 V power source.
The
µ
PA1814 features a low on-state resistance and
excellent switching characteristics, and is suitable for
applications such as power switch of portable machine
and so on.
8
PACKAGE DRAWING (Unit : mm)
5
1, 5, 8 : Drain
2, 3, 6, 7: Source
4
: Gate
1.2 MAX.
1.0±0.05
0.25
+5°
–3°
0.1±0.05
0.5
0.6
+0.15
–0.1
FEATURES
5
Can be driven by a 4 V power source
Low on-state resistance
R
DS(on)1
= 16 mΩ MAX. (V
GS
= –10 V, I
D
= –3.5 A)
R
DS(on)2
= 24 mΩ MAX. (V
GS
= –4.5 V, I
D
= –3.5 A)
R
DS(on)3
= 27 mΩ MAX. (V
GS
= –4.0 V, I
D
= –3.5 A)
Built-in G-S protection diode against ESD
1
4
0.145 ±0.055
3.15 ±0.15
3.0 ±0.1
6.4 ±0.2
4.4 ±0.1
1.0 ±0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power TSSOP8
0.65
0.27
+0.03
–0.08
0.8 MAX.
µ
PA1814GR-9JG
0.1
0.10 M
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Drain to Source Voltage
Gate to Source Voltage
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
EQUIVALENT CIRCUIT
–30
±20
±7.0
±28
2.0
150
–55 to +150
V
V
A
A
W
°C
°C
Gate
Protection
Diode
Source
Gate
Drain
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
T
ch
T
stg
Body
Diode
Total Power Dissipation
Channel Temperature
Storage Temperature
Notes 1.
PW
10
µ
s, Duty Cycle
1 %
2
2.
Mounted on ceramic substrate of 5000 mm x 1.1 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
D13804EJ1V0DS00 (1st edition)
Date Published June 1999 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1998, 1999

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