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IDT71321LA25JGI

Description
Dual-Port SRAM, 2KX8, 25ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52
Categorystorage    storage   
File Size134KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

IDT71321LA25JGI Overview

Dual-Port SRAM, 2KX8, 25ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52

IDT71321LA25JGI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeLCC
package instructionQCCJ, LDCC52,.8SQ
Contacts52
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionIDT IDT71321LA25JGI SRAM Memory, 16kbit, 4.5 → 5.5 V, 25ns 52-Pin PLCC
Maximum access time25 ns
Other featuresAUTOMATIC POWER DOWN
I/O typeCOMMON
JESD-30 codeS-PQCC-J52
JESD-609 codee3
length19.1262 mm
memory density16384 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals52
word count2048 words
character code2000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize2KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC52,.8SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Certification statusNot Qualified
Maximum seat height4.572 mm
Maximum standby current0.004 A
Minimum standby current2 V
Maximum slew rate0.22 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width19.1262 mm
Base Number Matches1
HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
Features
IDT71321SA/LA
IDT71421SA/LA
High-speed access
– Commercial: 20/25/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
– IDT71321/IDT71421SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT71321/421LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
Two
INT
flags for port-to-port communications
MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
On-chip port arbitration logic (IDT71321 only)
BUSY
output flag on IDT71321;
BUSY
input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
10L
A
0L
(1,2)
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
Address
Decoder
11
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2691 drw 01
(2)
NOTES:
1. IDT71321 (MASTER):
BUSY
is open drain output and requires pullup resistor of 270Ω.
IDT71421 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor of 270Ω.
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC-2691/13
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