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DPS1MX8MKN3-45C

Description
SRAM Module, 1MX8, 45ns, CMOS, CDMA32, 0.600 INCH, DIP-32
Categorystorage    storage   
File Size549KB,6 Pages
ManufacturerB&B Electronics Manufacturing Company
Download Datasheet Parametric View All

DPS1MX8MKN3-45C Overview

SRAM Module, 1MX8, 45ns, CMOS, CDMA32, 0.600 INCH, DIP-32

DPS1MX8MKN3-45C Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerB&B Electronics Manufacturing Company
Parts packaging codeMODULE
package instructionDIP, DIP32,.6
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time45 ns
I/O typeCOMMON
JESD-30 codeR-CDMA-T32
JESD-609 codee0
memory density8388608 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of ports1
Number of terminals32
word count1048576 words
character code1000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1MX8
Output characteristics3-STATE
ExportableNO
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.6
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.0006 A
Minimum standby current2 V
Maximum slew rate0.23 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Base Number Matches1
1Mx8, 20 - 45ns, STACK/DIP
30A129-12
B
8 Megabit High Speed CMOS SRAM
DPS1MX8MKN3
DESCRIPTION:
The DPS1MX8MKN3 High Speed SRAM ‘’STACK’’
devices are a revolutionary new memory subsystem
using Dense-Pac Microsystems’ ceramic Stackable
Leadless Chip Carriers (SLCC) mounted on a co-fired
ceramic substrate having side-brazed leads.
The
device packs 8-Megabits of low-power CMOS static
RAM in a 600-mil-wide, 32-pin dual-in-line package.
The DPS1MX8MKN3 STACK devices contain two
512K x 8 SRAM die, each packaged in a hermetically
sealed SLCC, making the devices suitable for
commercial, industrial and military applications.
By using SLCCs, the ‘’Stack’’ family of devices offer a
higher board density of memory than available with
conventional through-hole, surface mount or hybrid
techniques.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
Organizations Available:
1Meg x 8
Access Times:
20*, 25, 30, 35, 45ns
Fully Static Operation
- No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage:
2.0V min.
Package Available:
32 Pin DIP
*
Commercial and Industrial Grade only.
PIN-OUT DIAGRAM
PIN NAMES
A0 - A18
I/O0 - I/O7
CE0, CE1
WE
V
DD
V
SS
Address Inputs
Data Input/Output
Low Chip Enables
Write Enable
Power (+5V)
Ground
30A129-12
REV. B
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
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