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BS616LV1613FI

Description
Very Low Power/Voltage CMOS SRAM 1M X 16 bit
File Size253KB,8 Pages
ManufacturerBSI
Websitehttp://www.brilliancesemi.com/
Download Datasheet View All

BS616LV1613FI Overview

Very Low Power/Voltage CMOS SRAM 1M X 16 bit

BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
1M X 16 bit
(Dual CE Pins)
DESCRIPTION
BS616LV1613
• Vcc operation voltage :
2.7~3.6V
• Very low power consumption :
Vcc
= 3.0V
C-grade: 45mA (@55ns) operating current
I -grade: 46mA (@55ns) operating current
C-grade: 36mA (@70ns) operating current
I -grade: 37mA (@70ns) operating current
3.0uA (Typ.)
CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV1613 is a high performance, very low power CMOS Static
Random Access Memory organized as 1,048,576 words by 16 bits and
operates from a range of
2.7V to 3.6V
supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of
3.0uA
at
3.0V/25
o
C
and maximum access time of 55ns at
3.0V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616LV1613 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1613 is available in 48-pin BGA package.
PRODUCT FAMILY
PRODUCT FAMILY
OPERATING
TEMPERATURE
+0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
RANGE
2.7V ~ 3.6V
2.7V ~ 3.6V
SPEED
(ns)
55ns : 3.0~3.6V
70ns : 2.7~3.6V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PKG TYPE
Vcc=3V
Vcc=3V
55ns
Vcc=3V
70ns
BS616LV1613FC
BS616LV1613FI
55 / 70
55 / 70
10 uA
20 uA
45mA
46mA
36mA
37mA
BGA-48-0912
BGA-48-0912
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
2
OE
UB
D10
D11
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
D1
D3
D4
D5
WE
A11
6
CE2
D0
D2
VCC
VSS
D6
D7
NC
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 8192
8192
D0
16
Data
Input
Buffer
16
Column I/O
VCC
D14
D15
A 18
D12
D13
A19
.
A8
.
.
.
.
D15
CE2
CE1
WE
OE
UB
LB
Vcc
Vss
.
.
.
.
Write Driver
Sense Amp
512
Column Decoder
16
Data
Output
16
Buffer
18
Control
Address Input Buffer
A11 A10 A9 A8 A7 A6 A5 A18 A19
48-Ball CSP top View
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
R0201-BS616LV1613
1
Revision 1.1
Jan.
2004
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