PI74SSTU32866NBEX datasheet, PDF

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PI74SSTU32866NBEX: DescriptionRegister 25b 1:1 or 14b 1:2; Categorylogic logic; File Size493KB，18 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/; Environmental Compliance

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PI74SSTU32866NBEX Overview

PI74SSTU32866NBEX Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	BGA
package instruction	LFBGA, BGA96,6X16,32
Contacts	96
Reach Compliance Code	compli
ECCN code	EAR99
Other features	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE
series	SSTU
JESD-30 code	R-PBGA-B96
JESD-609 code	e1
length	13.5 mm
Logic integrated circuit type	D FLIP-FLOP
Humidity sensitivity level	3
Number of digits	25
Number of functions	1
Number of terminals	96
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA96,6X16,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
propagation delay (tpd)	2.35 ns
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	5.5 mm
minfmax	270 MHz

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PI74SSTU32866

25-bit 1:1 or 14-bit 1:2 Configurable

Registered Buffer with Parity

Product Features

• PI74SSTU32866 is a low-voltage device with V

= 1.8V

• Supports Low Power Standby Operation

• All Inputs are SSTL_18 Compatible, except RST, C0, C1,

which are LVCMOS.

• Output drivers are optimized to drive DDR-II DIMM loads

• Packaging (Pb-free & Green):

— 96-Ball LFBGA (NB)

• PI74SSTU32866 supports DDR2-533/400

Product Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with

parity is designed for 1.7 V to 1.9 V V

operation. All clock

and data inputs are compatible with the JEDEC standard for

SSTL_18. The control and reset (RST) inputs are LVCMOS. All

data outputs are 1.8 V CMOS drivers that have been optimized to

drive the DDR-II DIMM load, and meet SSTL_18 specifications.

The error (QERR) output is 1.8 V open-drain driver.

The PI74SSTU32866 operates from a differential clock (CK and

CK). Data are registered at the crossing of CK going high, and

CK going low.

The PI74SSTU32866 accepts a parity bit from the memory

controller on the parity bit (PAR_IN) input, compares it with

the data received on the DIMM-independent D-inputs (D2–D3,

D5–D6, D8–D25 when

C0 = 0 and C1 = 0; D2–D3, D5–D6, D8–D14 when C0 = 0 and

C1=1; or D1–D6, D8–D13 when C0 = 1 and C1=1) and indicates

whether a parity error has occurred on the open-drain QERR pin

(active low). The convention is even parity, i.e., valid parity is

defined as an even number of ones across the DIMM-independent

data inputs combined with the parity input bit. To calculate parity,

all DIMM-independent data inputs must be tied to a known logic

state.

When used as a single device, the C0 and C1 inputs are tied low.

In this configuration, parity is checked on the PAR_IN input

which arrives one cycle after the input data to which it applies.

The partial-parity-out (PPO) and QERR signals are valid three

cycles after the corresponding data inputs.

When used in pairs, the C0 input of the first register is tied low

and the C0 input of the second register is tied high. The C1 input

of both registers are tied high. Parity, which arrives one cycle

after the data input to which it applies, is checked on the PAR_IN

input of the first device. The PPO and QERR signals are produced

on the second device three clock cycles after the corresponding

data inputs. The PPO output of the first register is cascaded to

the PAR_IN of the second register. The QERR output of the first

on the QERR output of the second register.

If an error occurs and the QERR output is driven low, it stays

latched low for two clock cycles or until RST is driven low. The

DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are

not included in the parity check computation.

The C0 input controls the pinout configuration for the 1:2 pinout

from A configuration (when low) to B configuration (when high).

The C1 input controls the pinout configuration from 25-bit 1:1

(when low) to 14-bit 1:2 (when high).

In the DDR-II RDIMM application, RST is specified to be

completely asynchronous with respect to CK and CK. Therefore,

PS8739B

11/21/05

Logic Block Diagram 1:2 Mode (Positive Logic)

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PI74SSTU32866NBEX Related Products

	PI74SSTU32866NBEX	PI74SSTU32866NBX
Description	Register 25b 1:1 or 14b 1:2	D Flip-Flop, SSTU Series, 1-Func, 25-Bit, True Output, CMOS, PBGA96, MO-205CC, LFBGA-96
Is it lead-free?	Lead free	Contains lead
Is it Rohs certified?	conform to	incompatible
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	BGA	BGA
package instruction	LFBGA, BGA96,6X16,32	LFBGA, BGA96,6X16,32
Contacts	96	96
Reach Compliance Code	compli	compliant
ECCN code	EAR99	EAR99
Other features	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE
series	SSTU	SSTU
JESD-30 code	R-PBGA-B96	R-PBGA-B96
JESD-609 code	e1	e0
length	13.5 mm	13.5 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Number of digits	25	25
Number of functions	1	1
Number of terminals	96	96
Maximum operating temperature	70 °C	70 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA
Encapsulate equivalent code	BGA96,6X16,32	BGA96,6X16,32
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	240
power supply	1.8 V	1.8 V
propagation delay (tpd)	2.35 ns	2.35 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	NOT SPECIFIED
width	5.5 mm	5.5 mm
minfmax	270 MHz	270 MHz

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