or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1
xpio110_08
Lattice Semiconductor
Figure 1. XPIO 110GXS Block Diagram
XPIO 110GXS Data Sheet
RX_LOS_POL
LB_LVDS_Enb
RX_LV_EN
RX_CLK
RX_D_LV_P[0]
RX_D_LV_N[0]
.
.
.
RX_D_LV_P[15]
RX_D_LV_N[15]
RX_CK_LV_P
*
RX_CK_LV_N
RX_LV_CKDLY[1:0]
SC_LV_ISET[1:0]
Deserializer
1:16
DEMUX
Clock
Data
Recovery
1
0
0
LVDS
Output
0
1
Bit
Order
Logic
1
16
RX_LOS
RX_REF_CK_Enb
RX_REF_CK_P
RX_REF_CK_N
REF_CK_P
REF_CK_N
RX_D_RP_Enb
RX_D_RP_P
RX_D_RP_N
SC_LOCK_DIFF[1:0]
RX_FILT_EXT_P
RX_FILT_EXT_N
RX_LOCK
RX_LOCK2REFb
Serial
Data
SC_LSB1STb
Limiting
Amplifier
RX_D_P
RX_D_N
REF_CK_SEL
CK622OUT_P
CK622OUT_N
LB_P622_Enb
TX_D_LV_P[0]
TX_D_LV_N[0]
.
.
.
TX_D_LV_P[15]
TX_D_LV_N[15]
1
0
Bit
Order
Logic
16
1
0
CMU 622
Out
TX_CP_ISET[1:0]
Clock
Multiplier
Unit
TX_CK622_PA[1:0]
TX_LOCK
TX_FILT_EXT_P
TX_FILT_EXT_N
CK622OUT_SEL
LVDS
Input
TX_CLK
FIFO_WRITE_CK
TX
FIFO
Serializer
16:1 MUX
TX_LV_PLLBPb
0
1
FIFO_RD_CK
TX_FIFO_INIT
TX_FIFO_ERR
TX_CK_LV_P
TX_CK_LV_N
TX_CK_LV_PA[1:0]
TX_CK_LV_SEL
LVPLL
TX CML
DRIVER
TX_D_P
TX_D_N
TX_D_EN
TX_CML_ISET[1:0]
2
Lattice Semiconductor
XPIO 110GXS Data Sheet
The XPIO 110GXS is divided into a transmitter section and a receiver section. The major operations performed by
the chip are:
Transmitter Operation
1. Low jitter clock generation via the Clock-Multiplier-Unit (CMU)
2. 16-bit LVDS parallel data input
3. Parallel-to-serial conversion
10Gbps CML serial data output
Receiver Operation
1. CML serial input to a limiting amplifier
2. Clock and data recovery
3. Serial-to-parallel conversion
4. 16-bit LVDS parallel data output, with a synchronizing clock output
5. Built-in LVDS line loopback, and LVDS diagnostic loopback modes for testing and network diagnosis
Functional Description
The XPIO 110GXS transceiver is a low power, low jitter, and fully integrated serializer/deserializer chip. It operates
in the data rate range of 9.95-10.31 Gbps, performs all necessary parallel-to-serial and serial-to-parallel conver-
sions. The chip is suitable for applications utilizing OC-192 and 10GE. The serial interface I/O uses the CML stan-
dard while the low speed parallel I/O is based on the LVDS standard. These standards are compliant to both the
Optical Interface Forum's SFI-4 standard and the 10GE’s XSBI standard. The LVDS parallel I/O can be directly
connected to Multi-Standard-Agreement (MSA) 300 systems.
To accommodate bit order differences between OC-192 and 10GE, the XPIO 110GXS provides the capability of bit
swapping. The data presented on TX_D_LV_P/N[15] or MSB is transmitted first, followed in order by
TX_D_LV_P/N[14] to TX_D_LV_P/N[0] when SC_LSB1STb is not connected or is connected to a logic high.
TX_D_LV_P/N[0] or LSB is transmitted first followed in order by TX_D_LV_P/N[1] to TX_D_LV_P/N[15] when
SC_LSB1STb is connected to a logic low. The parallel receive bus mirrors this behavior. The SC_LSB1STb uncon-
nected, or at logic high, the first serial bit received is presented on RX_D_LV_P/N[15]. Conversely the first bit
received is presented on RX_D_LV_P/N[0] when SC_LSB1STb is pulled low.
Transmitter
The transmitter performs the serialization process, converting the 16-bit parallel LVDS data stream to a serial data
stream at approximately a 10 Gbps data rate. The transmitter consists of a LVDS data receiver, a FIFO, a 16:1 seri-
alizer, a low jitter CMU, and a 10Gbps output data driver.
LVDS Data Receiver
The Input and Analog Pin Assignments and Descriptions table in this document shows the 16 LVDS differential
data input pairs (TX_D_LV_P/N [15:0]). Data applied at the transmit data pairs is aligned to the LVDS input clock
(TX_CK_LV_P/N), which can be either 1/16th or 1/32nd the transmit data rate (622.08 or 311.04 nominally for OC-
192). The clock rate is selected through the assertion or deassertion of the TX_CK_LV_SEL pin. Figure 13
describes the LVDS data relationship to the LVDS input clock.
The LVDS input receivers convert the LVDS signals to CMOS signals. The converted signals are latched based on
an internal clock that is generated from the TX_CK_LV_P/N input clock through a phase-lock-loop (LVPLL). In
order to achieve optimal latch timing, the phase relationship between the internal clock and the TX_CK_LV_P/N
clock can be adjusted by programming TX_CK_LV_PA[1:0]. The LVDS PLL can also be bypassed by the assertion
of the TX_LV_PLLBPb pin, which is a desirable feature in some applications. When the LVPLL is bypassed it is up
to the system designer to manage the TX_CK_LV_P/N input.
Transmitter FIFO
A 16 bit wide and 8-word deep FIFO is designed into the XPIO 110GXS to decouple the LVDS clock from the serial
transmission clock. In addition, the FIFO also improves the tolerance to minor phase differences between the FIFO
write clock and read clock due to phase drift or phase wander.
3
Lattice Semiconductor
XPIO 110GXS Data Sheet
The FIFO circuitry indicates an overflow or underflow condition by asserting TX_FIFO_ERR high. The
TX_FIFO_ERR only provides status information about an overflow or underflow. It does not indicate which of the
two events actually occurred. During the period of time when the TX_FIFO_ERR signal is asserted, the TX_D_P/N
pins toggle at a constant rate. This prevents the AC coupling capacitors from becoming blocking capacitors.
The transmit FIFO’s read and write pointers can be recentered by asserting the TX_FIFO_INIT pin high. Thus, one
way to automatically recenter the FIFO read/write pointers after TX_FIFO_ERR is asserted is to connect
TX_FIFO_INIT and TX_FIFO_ERR together.
The FIFO read/write pointers are re-centered after:
• Device power on reset
• Transmitter reset (asserting RESET_TXb low)
• CMU PLL is out of lock
Serialization
The output data bus from the FIFO feeds a 16:1 serializer to generate a 9.953 Gbps (OC-192 rate) data stream.
The high-speed clock (TX_CLK) is a low jitter clock generated by the CMU. The serializer uses TX_CLK to clock
out high-speed data.
TX CML Driver
The serial data stream in turn becomes an input to a differential high-speed CML data driver. The TX_D CML driver
incorporates an internal 50-ohm termination resistor on both P and N branches for impedance matching with the
PCB transmission line. The CML output may require AC coupling (as in Figure 5). The output current of the CML
driver can be adjusted using two configuration pins, TX_CML_ISET[1:0]. These configuration pins are used to bal-
ance power consumption and performance.
In normal operation, the data presented at the LVDS TX inputs requires about nine clocks to transit the various
logic blocks before being presented at the TX CML driver output.
Clock-Multiplier-Unit (CMU)
The CMU consists of a differential PLL that is capable of producing a very low jitter serial clock. The clock is gener-
ated through a reference clock (REF_CLK_P/N) at either 1/16
th
or 1/64
th
the data transmission rate (This is nomi-
nally 622.08 or 155.52 MHz for OC-192 data rates). This reference clock must be generated from a differential
crystal oscillator that has a frequency accuracy of better than ±20ppm for SONET applications.
The CMU PLL can provide a phase-adjustable parallel data rate clock (CK622OUT_P/N) that is 1/16
th
the transmit
data rate to clock other devices or systems. The output of CK622OUT_P/N meets the LVDS signaling specifica-
tions. Using the TX_CK622_PA[1:0] configuration pins, the phase can be adjusted in T/4 increments, where T is the
period of the clock for the parallel interface.
Receiver
Limiting Amplifier
The XPIO 110GXS 10 Gbps CMOS receiver integrates a highly sensitive limiting amplifier. The XPIO 110GXS also
implements an amplifier offset compensation technology that works in conjunction with the limiting amplifier to
achieve superior amplifier input sensitivity. Sufficient gain is designed into the limiting amplifier to detect a peak-to-
peak differential input as small as 50mV. This attenuated signal can be properly detected and amplified to satura-
tion.
Clock and Data Recovery (CDR)
One of the most critical circuits in the receiver is the clock and data recovery (CDR) block. The CDR block extracts
the clock from an incoming high-speed, non-return to zero (NRZ) data, and retimes the data based on an external
reference clock. Extraction of the clock embedded in the serial data-stream is performed through comparison of the
phase relationship between transitions of the data and the external reference clock.
4
Lattice Semiconductor
XPIO 110GXS Data Sheet
The external reference clock is essential for the CDR block. The reference clock provides two functions: One func-
tion is training the VCO in the CDR PLL to the serial data-stream frequency. The other is to generate a stable clock
when the input serial data is absent. The CDR PLL creates an internal reference frequency. The reference fre-
quency is monitored, and a loss of lock is asserted when it goes out of specification.
Lock Detect
The XPIO 110GXS implements a CDR lock detector circuit that monitors the frequency of the internal clock.
RX_LOCK is asserted whenever a REF_CK or RX_REF_CK are operating within specification. RX_LOCK is deas-
serted under some specific circumstances:
1. When RX_RESETb is asserted (i.e. ‘0’)
2. When the REF_CK (or RX_REF_CK) is not present.
3. When the clock recovered from the incoming datastream falls outside the range specified by the
SC_LOCK_DIFF input pins. When the recovered clock is out of range, RX_LOCK will deassert briefly and then
be reasserted as it relocks to the REF_CK (RX_REF_CK). This effectively leaves the RX_LOCK signal toggling
as it attempts to reacquire the clock embedded in the RX_D_P/N data inputs.
Deserialization
The XPIO 110GXS uses a 1:16 demultiplexer to deserialize the high speed data from the CDR. The demultiplexer
generates the 16 bit parallel data stream. The bit order presented on the RX_D_LV_P/N[0..15] LVDS outputs mir-
rors the order on the TX_D_LV[0..15]P/N LVDS inputs. The first data bit received by the CDR is present on
RX_D_LV_P/N[15] when SC_LSB1STb is connected to a logic high, and it is present on RX_D_LV_P/N[0] when
SC_LSB1STb is connected to a logic low.
LVDS Data Transmitter
The 16-bit parallel data and clock are sent out via the RX_D_LV_P/N[0..15] and RX_LV_CK_P/N LVDS pins,
respectively. Data on the RX_D_LV_P/N pins is synchronous to the RX_LV_CK_P/N output pins. The data coming
in on the RX_D_P/N pins requires around five clocks to arrive at the RX_D_LV_P/N outputs. The output current of
the LVDS outputs is adjustable using the SC_LV_ISET[1:0] configuration pins. System designers can use these
pins to optimize the LVDS receive data performance.
XFP Module Considerations
The XPIO110GXS was conceived and implemented prior to the finalization of the XFP specification. The implica-
tion of this is the CML TX voltage swing is typically higher than that specified in the XFP MSA documents.
The XFP MSA specification indicates a XFP module should accept a maximum of 800mV input swing. In practice it
is the individual XFP module internal architecture that defines the maximum range. However, most XFP modules
simply rate themselves to the 800mV specification regardless of the likelihood they may operate beyond the range
specified in the XFP MSA.
Actual operation of the XPIO110GXS with existing XFP modules shows these still operate with the CML swing set
to the default TX_CML_ISET[1:0] = “11”. In order to more closely match the XFP specification a
TX_CML_ISET[1:0] = “01” configuration is recommended. This places the typical output swing from the CML TX
outputs at 650mV to 1100mV.
Loopback Operation
The XPIO 110GXS supports several loopback operations to provide diagnostic functions and to aid in performing
SONET/SDH functional tests.
LVDS Diagnostic Loopback
In LVDS loopback mode, 16 bit-wide data is fed into the TX LVDS input. The XPIO 110GXS routes data from the
LVDS transmit interface to the internal receiver interface, and then repeats the data at the LVDS RX output.
To enable this mode of operation set BIST_ENb=0, LB_LVDS_ENb=0, and BIST_LB_SC[1:0]=10.
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