HV9112
High-Voltage Current-Mode PWM Controller
Features
►
►
►
►
►
►
►
9.0 to 80V input voltage range
Current-mode control
High efficiency
Up to 1.0MHz internal oscillator
Internal start-up circuit
Low internal noise
50% maximum duty cycle
General Description
The Supertex HV9112 is a BiCMOS/DMOS single-output,
pulse width modulator IC intended for use in high-speed,
high-efficiency switch mode power supplies. It provides all the
functions necessary to implement a single-switch current mode
PWM, in any topology, with a minimum of external parts.
Because the HV9112 utilizes Supertex’s proprietary BiCMOS/
DMOS technology, it requires less than one tenth of the operating
power of conventional bipolar PWM ICs, and can operate at
more than twice their switching frequency. The dynamic range
for regulation is also increased, to approximately 8 times that
of similar bipolar parts. It starts directly from any DC input
voltage between 9.0 and 80VDC, requiring no external power
resistor. The output stage is push-pull CMOS and thus requires
no clamping diodes for protection, even when significant lead
length exists between the output and the external MOSFET. The
clock frequency is set with a single external resistor.
Accessory functions are included to permit fast remote shutdown
(latching or nonlatching) and under voltage shutdown.
For similar ICs intended to operate directly from up to 450VDC
input, please consult the data sheets for the HV9120 and
HV9123.
For detailed circuit and application information, please refer to
application notes AN-H13 and AN-H21 to AN-H24.
Applications
►
►
►
►
►
DC/DC converters
Distributed power systems
ISDN equipment
PBX systems
Modems
Functional Block Diagram
FB
14
COMP
13
OSC
IN
8
OSC
OUT
7
Error
Amplifier
10
–
OSC
2V
VREF
+
4V
–
Modulator
Comparator
T
Q
To VDD
4
REF
GEN
+
+
–
Current Limit
Comparator
R
S
Q
OUTPUT
5
-VIN
BIAS
VDD
+VIN
1
6
2
Current
Sources
To
Internal
Circuits
1.2V
3
VDD
SENSE
–
–
8.1V
8.6V
Undervoltage
Comparator
+
Q
S
R
11
SHUTDOWN
12
RESET
+
Pre-regulator/Startup
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV9112
Ordering Information
14-Lead Narrow Body SOIC
Device
HV9112
8.65x3.90mm body
1.75mm height (max)
1.27mm pitch
HV9112NG-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
OSC IN
NC
Absolute Maximum Ratings
Parameter
Input voltage, V
IN
Logic voltage, V
DD
Logic linear input,
FB and sense input voltage
Storage temperature
Power dissipation
Value
80V
15.5V
-0.3V to V
DD
+0.3V
-65°C to +150°C
750mW
SHUTDOWN
RESET
COMP
FB
VREF
OSC OUT
VDD
-VIN
OUTPUT
SENSE
+VIN
BIAS
14-Lead Narrow Body SOIC (NG)
Stresses beyond those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Product Marking
Top Marking
YWW
HV9112NG
LLLLLLLL
Bottom Marking
CCCCCCCCC AAA
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
14-Lead Narrow Body SOIC (NG)
Electrical Characteristics
Sym
Reference
V
REF
Z
OUT
I
SHORT
ΔV
REF
Oscillator
f
MAX
f
OSC
-
-
Oscillator frequency
Initial accuracy
1
Voltage stability
Temperature coefficient
Output voltage
Output impedence
Short circuit current
Parameter
(Unless otherwise specified, V
DD
= 10V, +V
IN
= 48V, -V
IN
= 0V, R
BIAS
= 390KΩ, R
OSC
= 330KΩ, T
A
= 25°C.)
#
-
#
-
#
-
-
-
-
#
Min
3.88
15
-
-
1.0
80
160
-
-
Typ
4.00
30
125
0.25
3.0
100
200
-
170
Max
4.12
45
250
-
-
120
240
15
-
Units
V
KΩ
μA
mV/°C
MHz
KHz
%
ppm/°C
Conditions
R
L
= 10MΩ
---
V
REF
= -V
IN
T
A
= -55°C to 125°C
R
OSC
= 0Ω
R
OSC
= 330KΩ
R
OSC
= 150KΩ
9.5V< V
DD
<13.5V
T
A
= -55°C to 125°C
Change in V
REF
with temperature
Notes:
# Guaranteed by design.
1. Stray capacitance on OSC In pin must be ≤5.0pF.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV9112
Electrical Characteristics
(cont.)
Sym
PWM
D
MAX
D
MIN
Maximum duty cycle
Minimum duty cycle
Maximum pulse width before
pulse drops out
Maximum input signal
t
D
V
FB
I
IN
V
OS
A
VOL
GB
Z
OUT
I
SOURCE
I
SINK
PSRR
Delay to output
Feedback voltage
Input bias current
Input offset voltage
Open loop voltage gain
Unity gain bandwidth
Out impedance
Output source current
Output sink current
Power supply rejection
Error Amplifier
-
-
-
#
#
#
-
-
#
-1.4
0.12
3.92
-
60
1.0
4.00
25
80
1.3
see Fig. 1
-2.0
0.15
see Fig. 2
-
-
4.08
500
-
-
V
nA
-
dB
MHz
Ω
mA
mA
dB
V
FB
shorted to COMP
V
FB
= 4.0V
---
---
---
---
V
FB
= 3.4V
V
FB
= 4.5V
---
#
-
#
49.0
-
-
49.4
-
80
49.6
0
125
%
%
ns
---
---
---
Parameter
(Unless otherwise specified, V
DD
= 10V, +V
IN
= 48V, -V
IN
= 0V, R
BIAS
= 390KΩ, R
OSC
= 330KΩ, T
A
= 25°C.)
#
Min
Typ
Max
Units
Conditions
Current Limit
-
#
1.0
-
1.2
80
1.4
120
V
ns
V
FB
= 0V
V
SENSE
= 1.5V, V
COMP
≤ 2.0V
nulled during trim
Pre-regulator/Startup
+V
IN
+I
IN
V
TH
V
LOCK
Supply
I
DD
I
Q
I
BIAS
V
DD
Supply current
Quiescent supply current
Nominal bias current
Operating range
-
-
-
-
-
-
-
9.0
0.75
0.55
20
-
1.0
-
-
13.5
mA
mA
μA
V
C
L
< 75pF
SHUTDOWN = -V
IN
---
---
Input voltage
Input leakage current
V
DD
pre-regulator turn-off
threshold voltage
Undervoltage lockout
-
-
-
-
9.0
-
8.0
7.0
-
-
8.7
8.1
80
10
9.4
8.9
V
μA
V
V
I
IN
< 10µA; V
CC
> 9.4V
V
DD
> 9.4V
I
PREREG
= 10µA
---
Note:
# Guaranteed by design.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV9112
Electrical Characteristics
(cont.)
Sym
t
SD
t
SW
t
RW
t
LW
V
IL
V
IH
I
IH
I
IL
Output
V
OH
V
OL
Output high voltage
Output low voltage
Pull up
R
OUT
Output resistance
Pull down
Pull up
Pull down
t
R
t
F
Rise time
Fall time
-
-
-
-
-
-
#
#
V
DD
-0.3
-
-
-
-
-
-
-
-
-
15
8.0
20
10
30
20
-
0.2
25
20
30
30
75
75
V
V
Ω
Ω
ns
ns
I
OUT
= 10mA
I
OUT
= -10mA
I
OUT
= ±10mA
I
OUT
= ±10mA,
T
A
= -55°C to 125°C
C
L
= 500pF
C
L
= 500pF
Parameter
SHUTDOWN delay
SHUTDOWN pulse width
RESET pulse width
Latching pulse width
Input low voltage
Input high voltage
Input current, input high voltage
Input current, input low voltage
Shutdown Logic
#
#
#
#
-
-
-
-
-
50
50
25
-
7.0
-
-
50
-
-
-
-
-
1.0
-25
100
-
-
-
2.0
-
5.0
-35
ns
ns
ns
ns
V
V
μA
μA
---
SHUTDOWN and RESET low
---
---
V
IN
= V
DD
V
IN
= 0V
C
L
= 500pF, V
SENSE
= -V
IN
(Unless otherwise specified, V
DD
= 10V, +V
IN
= 48V, -V
IN
= 0V, R
BIAS
= 390KΩ, R
OSC
= 330KΩ, T
A
= 25°C.)
#
Min
Typ
Max
Units
Conditions
Note:
# Guaranteed by design.
Truth Table
SHUTDOWN
H
H
L
L
L→H
RESET
H
H→L
H
L
L
Output
Normal operation
Normal operation, no change
Off, not latched
Off, latched
Off, latched, no change
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
HV9112
Test Circuits
Error Amp Z
OUT
+10V
(V
DD
)
1.0V swept 100Hz – 2.2MHz
60.4K
(FB)
Reference
GND
(–V
IN
)
0.1µF
–
+
0.1V swept 10Hz – 1MHz
PSRR
100K1%
10.0V
4.00V
100K1%
–
+
V
1
V
1
Tektronix
P6021
(1 turn
secondary)
V
2
Reference
40.2K
V
2
0.1µF
NOTE:
Set Feedback Voltage so that V
COMP
= V
DIVIDE
± 1.0mV before
connecting transformer
Detailed Description
The preregulator/startup circuit for the HV9112 consists of
a high-voltage n-channel depletion-mode DMOS transis-
tor driven by an error amplifier to form a variable current
path between the VIN terminal and the VDD terminal. The
maximum current (about 20 mA) occurs when V
DD
= 0, with
current reducing as V
DD
rises. This path shuts off altogether
when V
DD
rises to somewhere between 7.8 and 9.4V, so that
if V
DD
is held at 10 or 12V by an external source(generally the
supply the chip is controlling). No current other than leakage
is drawn through the high voltage transistor. This minimizes
dissipation.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
C
STORAGE
≥ 100 x (gate charge of FET at 10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable.
A common resistor divider string is used to monitor V
DD
for
both the under voltage lockout circuit and the shutoff circuit
of the high voltage FET. Setting the under voltage sense
point about 0.6V lower on the string than the FET shutoff
point guarantees that the under voltage lockout always re-
leases before the FET shuts off.
Preregulator
Bias Circuit
An external bias resistor, connected between the BIAS pin
and VSS is required by the HV9112 to set currents in a se-
ries of current mirrors used by the analog sections of the
chip. The nominal external bias current requirement is 15 to
20µA, which can be set by a 390KΩ to 510KΩ resistor if a
10V V
DD
is used, or a 510kΩ to 680KΩ resistor if V
DD
will be
12V. A precision resistor is not required; ± 5% is fine.
Clock Oscillator
The clock oscillator of the HV9112 consists of a ring of
CMOS inverters, timing capacitors, and, a frequency divid-
ing flip-flop. A single external resistor between the OSC IN
and OSC OUT is required to set the oscillator frequency (see
graph). One major difference exists between the Supertex
HV9112 and competitive 9112s. On the Supertex part, the
oscillator is shut off when a shutoff command is received.
This saves about 150µA of quiescent current, which aids in
the construction of power supplies that meet CCITT specifi-
cation I-430, and in other situations where an absolute mini-
mum of quiescent power dissipation is required.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
