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NSBC114YDXV6T5

Description
Digital transistor 100ma 50v dual npn
CategoryDiscrete semiconductor    The transistor   
File Size79KB,9 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
Download Datasheet Parametric View All

NSBC114YDXV6T5 Overview

Digital transistor 100ma 50v dual npn

NSBC114YDXV6T5 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerON Semiconductor
package instructionLEAD FREE, PLASTIC, CASE 463A-01, 6 PIN
Contacts6
Manufacturer packaging codeCASE 463A-01
Reach Compliance Codeunknow
ECCN codeEAR99
Other featuresBUILT IN BIAS RESISTOR RATIO 4.7
Maximum collector current (IC)0.1 A
Collector-emitter maximum voltage50 V
ConfigurationSEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE)80
JESD-30 codeR-PDSO-F6
JESD-609 codee3
Humidity sensitivity level1
Number of components2
Number of terminals6
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Polarity/channel typeNPN
Maximum power dissipation(Abs)0.5 W
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin (Sn)
Terminal formFLAT
Terminal locationDUAL
Maximum time at peak reflow temperature40
transistor applicationsSWITCHING
Transistor component materialsSILICON
NSBC114EDXV6T1,
NSBC114EDXV6T5
Preferred Devices
Dual Bias Resistor
Transistors
NPN Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSBC114EDXV6T1
series, two BRT devices are housed in the SOT−563 package which is
ideal for low power surface mount applications where board space is at
a premium.
Features
(3)
R
1
Q
1
Q
2
R
2
(4)
R
1
(5)
NSBC114EDXV6T1
(6)
http://onsemi.com
(2)
R
2
(1)
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Lead−Free Solder Plating
These are Pb−Free Devices
1
MARKING
DIAGRAM
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted, common for Q
1
and Q
2
)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
50
50
100
Unit
Vdc
Vdc
mAdc
SOT−563
CASE 463A
PLASTIC
xx M
G
1
xx = Device Code (Refer to Page 2)
M = Date Code
G
= Pb−Free Package
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation; T
A
= 25°C
Derate above 25°C
Thermal Resistance, Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation; T
A
= 25°C
Derate above 25°C
Thermal Resistance, Junction-to-Ambient
Junction and Storage Temperature
Range
1. FR−4 @ Minimum Pad
ORDERING INFORMATION
Symbol
P
D
R
qJA
Symbol
P
D
R
qJA
T
J
, T
stg
Max
357 (Note 1)
2.9 (Note 1)
350 (Note 1)
Max
500 (Note 1)
4.0 (Note 1)
250 (Note 1)
−55 to +150
Unit
mW
mW/°C
°C/W
Unit
mW
mW/°C
°C/W
°C
NSBC1xxxDXV6T5G SOT−563* 8000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Device
NSBC1xxxDXV6T1
Package
Shipping
SOT−563* 4000/Tape & Reel
NSBC1xxxDXV6T1G SOT−563* 4000/Tape & Reel
NSBC1xxxDXV6T5
SOT−563* 8000/Tape & Reel
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
May, 2006 − Rev. 6
Publication Order Number:
NSBC114EDXV6/D
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