DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Rev. 02 — 13 August 2008
Product data sheet
1. General description
The DAC1003D160 is optimized to reduce architecture complexity and overall system
cost. The Digital-to-Analog Converter (DAC) leads dynamic performance in multi-carrier
support because of its direct IF conversion capabilities. With an internal sampling rate up
to 160 MHz, the DAC1003D160 is an extremely competitive solution for broadband
wireless systems transmitters, as well as a wide range of applications.
2. Features
I
I
I
I
I
I
I
I
I
I
Dual 10-bit resolution
Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz
Input data rate up to 80 MHz
2
×
interpolation filter
Output data rate up to 160 Mhz
Single 3.3 V power supply
Low noise capacitor free integrated Phase-Locked Loop (PLL)
Low power dissipation
HTQFP80 package
Ambient temperature from
−40 °C
to +85
°C
3. Applications
I
I
I
I
I
I
Broadband wireless systems
Digital radio links
Cellular base stations
Instrumentation
Cable modems
Cable Modem Termination System (CMTS)/Data Over Cable Service Interface
Specification (DOCSIS)
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
4. Ordering information
Table 1.
Ordering information
Package
Name
DAC1003D160HW
HTQFP80
Description
plastic thermal enhanced thin quad flat package; 80 leads;
body 12
×
12
×
1 mm; exposed die pad
Version
SOT841-1
Type number
5. Block diagram
DAC1003D160
V
CCA
U/I
60
IVIRES
I9 to I0
11 to 16,
19 to 22
10
73
LATCH
10
FIR
10
DAC
72
IOUT
IOUTN
(CLK
×
2)
CLK
CLKN
5
6
CLOCK
DRIVER
PLL
(CLK
×
2)
INTERNAL
BAND GAP
58
57
DAC
69
68
GAPOUT
GAPD
QOUT
QOUTN
(CLK
×
2)
Q9 to Q0
31 to 34,
37 to 42
10
LATCH
10
FIR
10
i.c.
V
CCD
2, 8
10, 51
(1)
(2)
(3)
(4)
U/I
V
CCA
59
QVIRES
V
CCA
014aaa532
AGND DGND
DEC
(1) Pins 1, 3, 61, 65, 76 and 80.
(2) Pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77 and 79.
(3) Pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55 and 56.
(4) Pins 18, 26, 36, 43, 63 and 78.
Fig 1. Block diagram
DAC1003D160_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 August 2008
2 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
6. Pinning information
6.1 Pinning
68 QOUTN
72 IOUTN
80 V
CCA
79 AGND
77 AGND
75 AGND
74 AGND
71 AGND
70 AGND
69 QOUT
67 AGND
66 AGND
64 AGND
62 AGND
76 V
CCA
65 V
CCA
73 IOUT
78 DEC
V
CCA
i.c.
V
CCA
AGND
CLK
CLKN
AGND
i.c.
DGND
1
2
3
4
5
6
7
8
9
63 DEC
61 V
CCA
60 IVIRES
59 QVIRES
58 GAPOUT
57 GAPD
56 DGND
55 DGND
54 DGND
53 DGND
52 DGND
51 V
CCD
50 DGND
49 DGND
48 n.c.
47 n.c.
46 n.c.
45 n.c.
44 DGND
43 DEC
42 Q0
41 Q1
Q2 40
014aaa533
© NXP B.V. 2008. All rights reserved.
V
CCD
10
I9 11
I8 12
I7 13
I6 14
I5 15
I4 16
DGND 17
DEC 18
I3 19
I2 20
I1 21
I0 22
n.c. 23
n.c. 24
DGND 25
DEC 26
n.c. 27
DGND
DAC1003D160
n.c. 28
DGND 29
DGND 30
Q9 31
Q8 32
Q7 33
Q6 34
DGND 35
DEC 36
Q5 37
Q4 38
Fig 2. Pin configuration
6.2 Pin description
Table 2.
Symbol
V
CCA
i.c.
V
CCA
AGND
CLK
CLKN
AGND
i.c.
DGND
DAC1003D160_2
Pin description
Pin
1
2
3
4
5
6
7
8
9
Type
[1]
S
I/O
S
G
I
I
G
O
G
Description
analog supply voltage
internally connected; leave open
analog supply voltage
analog ground
clock input
complementary clock input
analog ground
internally connected; leave open
digital ground
Product data sheet
Rev. 02 — 13 August 2008
Q3 39
3 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Pin description
…continued
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
23
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Type
[1]
S
I
I
I
I
I
I
G
O
I
I
I
I
I
I
G
O
I
I
G
G
I
I
I
I
G
O
I
I
I
I
I
I
O
G
I
I
I
I
G
G
Description
digital supply voltage
I data input bit 9 (Most Significant Bit (MSB))
I data input bit 8
I data input bit 7
I data input bit 6
I data input bit 5
I data input bit 4
digital ground
decoupling node
I data input bit 3
I data input bit 2
I data input bit 1
I data input bit 0 (Least Significant Bit (LSB))
not connected
not connected
digital ground
decoupling node
not connected
not connected
digital ground
digital ground
Q data input bit 9 (MSB)
Q data input bit 8
Q data input bit 7
Q data input bit 6
digital ground
decoupling node
Q data input bit 5
Q data input bit 4
Q data input bit 3
Q data input bit 2
Q data input bit 1
Q data input bit 0 (LSB)
decoupling node
digital ground
not connected
not connected
not connected
not connected
digital ground
digital ground
© NXP B.V. 2008. All rights reserved.
Table 2.
Symbol
V
CCD
I9
I8
I7
I6
I5
I4
DGND
DEC
I3
I2
I1
I0
n.c.
n.c.
DGND
DEC
n.c.
n.c.
DGND
DGND
Q9
Q8
Q7
Q6
DGND
DEC
Q5
Q4
Q3
Q2
Q1
Q0
DEC
DGND
n.c.
n.c.
n.c.
n.c.
DGND
DGND
DAC1003D160_2
Product data sheet
Rev. 02 — 13 August 2008
4 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Pin description
…continued
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Type
[1]
S
G
G
G
G
G
I
I/O
I
I
S
G
O
G
S
G
G
O
O
G
G
O
O
G
G
S
G
O
G
S
Description
digital supply voltage
digital ground
digital ground
digital ground
digital ground
digital ground
internal band gap power disable input
band gap output voltage
Q DAC biasing resistor
I DAC biasing resistor
analog supply voltage
analog ground
decoupling node
analog ground
analog supply voltage
analog ground
analog ground
complementary Q DAC output current
Q DAC output current
analog ground
analog ground
complementary I DAC output current
I DAC output current
analog ground
analog ground
analog supply voltage
analog ground
decoupling node
analog ground
analog supply voltage
Table 2.
Symbol
V
CCD
DGND
DGND
DGND
DGND
DGND
GAPD
GAPOUT
QVIRES
IVIRES
V
CCA
AGND
DEC
AGND
V
CCA
AGND
AGND
QOUTN
QOUT
AGND
AGND
IOUTN
IOUT
AGND
AGND
V
CCA
AGND
DEC
AGND
V
CCA
[1]
Type description: S: Supply; G: Ground; I: Input; O: Output.
DAC1003D160_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 August 2008
5 of 19
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