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SMSC COM20020I 3.3V Rev.E
Page 2
Revision 09-11-06
DATASHEET
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
TABLE OF CONTENTS
CHAPTER 1
CHAPTER 2
CHAPTER 3
CHAPTER 4
4.1
4.2
4.2.1
4.3
4.4
4.5
4.6
GENERAL DESCRIPTION................................................................................................................5
Figure 2 - Multiplexed, 8051-Like Bus Interface With RS-485 Interface.......................................................................16
Figure 3 - Non-Multiplexed, 6801-Like Bus Interface With RS-485 Interface ...............................................................17
Figure 4 - High Speed Cpu Bus Timing - Intel CPU Mode ...........................................................................................18
Figure 5 - COM20020I 3V Network Using RS-485 Differential Transceivers..................................................................20
Figure 6 - Dipulse Waveform For Data Of 1-1-0...........................................................................................................20
Figure 29 - Effect Of The EF Bit On The TA/RI Bit.......................................................................................................66
Figure 30 - Example Of Interface Circuit Diagram To ISA Bus ....................................................................................68
LIST OF TABLES
Table 1 - Typical Media ................................................................................................................................................23
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