it requires less than one tenth of the operating power of
conventional bipolar PWM ICs. Dynamic range for regulation
is also increased to approximately 8 times that of similar
bipolar parts. It operates directly from any DC input voltage
between 15 and 250 VDC. The START and STOP input
voltage thresholds can be programmed within the operating
input voltage range by means of a resistor divider, provided
+V
IN(START)
> +V
IN(STOP)
. The output stage is push-pull CMOS,
eliminating the need for external clamping diodes. The clock
frequency is set with a single external resistor.
❑
Distributed power systems
❑
DC/DC converters
+
48V INPUT
-
+
+
40V
+ ISOLATED
OUTPUT
-
RESET
TN2124K1
or
TN2524N8
+5.0V
REFERENCED
TO INPUT (-)
TERMINAL
RT
REF
NI
FB
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
HV9605C
Ordering Information
+V
IN
Min
15V
Max
250V
Feedback
Accuracy
< ± 1%
Max
Duty Cycle
49%
14 Pin
Plastic DIP
HV9605CP
Package Options
14 Pin
Narrow Body SOIC
HV9605CNG
Die
HV9605CX
Absolute Maximum Ratings*
Supply Voltage, V
DD
Operating Temperature Range
Storage Temperature Range
Power Dissipation @ 25°C, SOIC
Power Dissipation @ 25°C, Plastic DIP
*All voltages referenced to GND
-0.5V to +10V
-40°C to +85°C
-65°C to +150°C
Electrical Characteristics
Symbol
Parameters
O
bs
Pre-Regulator/Start-Up
+V
IN
+I
IN
+I
IN
+I
IN
+I
START
V
DD
UVLO
HYST
Regulator input voltage
Input leakage current
Input leakage current
Input leakage current
Pre-regulator start-up current
Regulator output voltage
Under voltage lockout threshold
Under voltage hysteresis
Supply
V
DD
I
DD
Operating range
Supply current
4.7
0.9
8.0
1.3
V
mA
OUT open,
f
OUT
= 20KHz to 150KHz,
V
DD
= 5V
Start/Stop Control
V
START
I
START
I
STOP
V
CLAMP
Start threshold
Start input current
Stop input current
Zener clamp voltage on STOP Pin
15
2
6.72
7.30
7.88
0.05
0.05
V
µA
µA
V
+V
IN
= 18V
+V
IN
= 18V
ol
et
e
750mW
1000mW
Min
Typ
Max
Unit
Conditions
15
250
6.0
15
70
5.0
4.4
4.1
0.1
4.5
4.2
0.3
4.6
4.4
0.4
V
µA
µA
µA
mA
V
V
V
V
DD
rising
+V
IN
=20V, Start=0V, Stop=0V
+V
IN
= 50V, V
DD
= 4.7V
+V
IN
= 250V, V
DD
= 4.7V
+V
IN
= 15V,
Start & Stop 10M½ to + V
IN
+V
IN
, Input Voltage
-0.5V to +250V
HV9605C
Electrical Characteristics
Symbol
Parameters
(continued)
Min
Typ
Max
Unit
Conditions
MOSFET Driver Output
V
OUT(HIGH)
V
OUT(LOW)
t
R
t
F
Output high voltage
Output low voltage
Rise time
Fall time
4.85
4.90
0.05
30
20
0.15
50
50
V
V
nsec
nsec
I
OUT
= 10mA, V
DD
= 5.00V
I
OUT
= -10mA
C
L
= 250pf
C
L
= 250pf
Oscillator
f
OUT
Output converter frequency
45
31.5
18
T
C
Ðf/f
Temperature coefficient
Voltage stability
D
MAX
D
MIN
Maximum duty cycle
Minimum duty cycle
ol
49.0
80
1.225
1.250
1.0
2.0
1.207
1.250
3.0
0.5
0.6
0.7
90
1.238
1.250
25
5.0
0
65
1.0
90
1.5
-2
2
50
3
4
72
PWM
Minimum pulse width before pulse drop out
Reference
V
REF
V
REF
V
REF
V
REF
I
REF(SHORT)
Reference output voltage
Load regulation
Line regulation
O
bs
Reference output voltage
Long term stability
Short circuit current
Current Sensing
V
CS
V
CS (LIMIT)
t
DELAY
Usable control current sense range
Current limit threshold
Current limit delay to output
Error Amplifier
V
FB
I
FB
or I
NI
V
OS
V
CM
A
VOL
BW
I
SOURCE
I
SINK
PSRR
Feedback voltage
Input bias current
Input offset voltage
Common mode input range
Open loop voltage gain
Unity gain bandwidth
Output current sourcing
Output current sinking
Power supply rejection
1.263
200
25
V
DD
-1
V
nA
mV
V
dB
MHz
-1
mA
mA
dB
V
FB
< V
NI
V
FB
> V
NI
4.5V < V
DD
< 5.5V, f=1KHz
REF shorted to NI, FB
shorted to Comp, T
A
= 25°C
V
FB
= 3.0V, V
NI
= 2.5V
et
e
150
50
KHz
55
KHz
35
38.5
22
KHz
20
KHz
100
1
300
3
PPM/⋅C
%
49.9
0
125
%
%
nsec
1.275
5.0
5.0
1.293
V
mV
mV
V
mV
1.0
mA
V
CS
(limit)
0.8
120
V
V
nsec
R
T
= 91K½
R
T
= 357K½
R
T
= 536K½
R
T
= 1.0M½
f
OUT
= 50KHz
f
OUT
= 50KHz, 4.5V< V
DD
<5.5V
f
OUT
= 20KHz
T
A
= 25⋅C
0 < I
REF
< 0.3mA
3.0V < V
DD
< 5.5V
-40⋅C < T
A
< 85⋅C
T
A
= 125⋅C, 1000hrs
V
REF
= SGND
V
CS
= 1.5V
HV9605C
Electrical Characteristics
Symbol
Parameters
(continued)
Min
Typ
Max
Unit
Conditions
Status Output
I
SINK
I
SOURCE
V
STATUS(LOW)
Output current sinking
Output current sourcing
5.0
5.0
V
DD
-0.2
1.0
0.02
t
R
Rise time
1.0
5.0
10
10
15
V
DD
2.0
0.04
mA
µA
V
V
V
msec
No load
Sinking 5mA
Sinking 100µA
4.7nF From Status to GND
V
STATUS
= 2.0V
V
STATUS(HIGH)
High output voltage
Low output voltage
Pin Description
SGND
–
Common connection for all low level signal and
digital circuits. While SGND and PGND must be
electrically connected together, having separate
common pins enhances the ability of the designer
to prevent coupling of noise into critical circuits.
ol
NI
REF
RT
4
PGND
–
bs
This pin provides common return for the high
transient current of the output driver circuits. While
PGND and SGND must be electrically connected,
having a separate connection prevents common
noise created by the high transient currents of the
output driver from being injected into critical circuits.
This is the start-up linear pre-regulator input which
can accept DC input voltages in the range of 15V
to 250V. With START and STOP set to more than
20V, the leakage current on this pin is less than
6.0µA at +V
IN
= 20V.
The resistive divider from +V
IN
sets the start voltage.
The resistive divider from +V
IN
sets the stop voltage.
+V
IN
–
START
STOP
V
DD
–
–
–
This is the supply pin for the PWM circuits. When
the input voltage to the +V
IN
pin exceeds the start
voltage the input regulator seeks to regulate the
voltage on the capacitor connected to this pin to a
nominal 4.5V.
This high current push-pull CMOS output is intended
to drive the gate of a power MOSFET. In order to
protect the power MOSFET in high electrical noise
environment, this output appears as low impedance
to PGND when V
DD
is at zero volts.
This is the current sense input to the PWM
comparators. Under normal operation the over
current limit is triggered when the voltage on this
pin is at 0.70V and the loop control operating peak
current may be set to any level below this, typically
in the range of 0.2 to 0.5V.
OUT
–
CS
–
O
et
e
COMP
FB
–
–
–
–
–
STATUS –
The low impedance output of the error amplifier.
The high impedance inverting input of the error
amplifier.
The high impedance non-inverting input of the error
amplifier.
This pin provides a 2% accuracy 1.25V low output
impedance buffered reference which is current
limited to 0.5mAmps and should be bypassed,
REF to SGND, with a 0.1µF ceramic capacitor.
The resistor connected from this pin to SGND sets
the frequency of the internal oscillator by setting
the charging current for the internal timing capacitor.
The oscillator frequency is twice the PWM output
frequency.
This output is held low until the +V
IN
voltage reaches
the programmed START voltage. It remains low
until the bootstrap supply to V
DD
forces the voltage
above the internal regulator set point. It is further
held low while the control amplifier output on the
COMP pin is forced to its high limit by a low output
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