ADC1610S series
Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
CMOS or LVDS DDR digital outputs
Rev. 02 — 12 April 2010
Objective data sheet
1. General description
The ADC1610S is a single-channel 16-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1610S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
because of a separate digital output supply. It supports the Low Voltage Differential
Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also
includes a SPI programmable full-scale to allow flexible input voltage range from
1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to
input frequencies of 170 MHz or more, the ADC1610S is ideal for use in communications,
imaging and medical applications.
2. Features and benefits
SNR, 72.5 dBFS; SFDR, 88 dBc
Sample rate up to 125 Msps
16-bit pipelined ADC core
Clock input divider by 2 for less jitter
contribution
Single 3 V supply
Flexible input voltage range: 1 V to 2 V
(peak-to-peak).
CMOS or LVDS DDR digital outputs
Power-down and Sleep modes
Input bandwidth, 600 MHz
Power dissipation, 430 mW at 80 Msps
Serial Peripheral Interface (SPI)
Duty cycle stabilizer
Fast OuT of Range (OTR) detection
INL
±1
LSB, DNL
±0.5
LSB
Offset binary, two’s complement, gray
code
HVQFN40 package
3. Applications
Wireless and wired broadband
communications
Spectral analysis
Ultrasound equipment
Portable instrumentation
Imaging systems
Software define radio
NXP Semiconductors
ADC1610S series
ADC1610S series; CMOS or LVDS DDR digital output
4. Ordering information
Table 1.
Ordering information
f
s
(Msps) Package
Name
ADC1610S125HN/C1 125
ADC1610S105HN/C1 105
ADC1610S080HN/C1 80
ADC1610S065HN/C1 65
Description
Version
SOT618-6
SOT618-6
SOT618-6
SOT618-6
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
×
6
×
0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
×
6
×
0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
×
6
×
0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
×
6
×
0.85 mm
Type number
5. Block diagram
SDIO/ODS
SCLK/DFS
CS
ADC1610S
ERROR
CORRECTION AND
DIGITAL
PROCESSING
SPI INTERFACE
OTR
CMOS:
D15 to D0
or
LVDS/DDR:
D15_M to D0_M
D15_P to D0_P
CMOS:
DAV
or
LVDS/DDR:
DAVP
DAVM
INP
T/H
INPUT
STAGE
INM
ADC CORE
16-BIT
PIPELINED
OUTPUT
DRIVERS
OUTPUT
DRIVERS
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
PWD
OE
CLKP
CLKM
VCM
SENSE
REFT
VREF
REFB
005aaa156
Fig 1. Block diagram
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
2 of 38
NXP Semiconductors
ADC1610S series
ADC1610S series; CMOS or LVDS DDR digital output
6. Pinning information
6.1 Pinning
36 SCLK/DFS
37 SDIO/DCS
31 D0_D1_M
30 D2_D3_P
29 D2_D3_M
28 D4_D5_P
27 D4_D5_M
26 D6_D7_P
25 D6_D7_M
24 D8_D9_P
23 D8_D9_M
22 D10_D11_P
21 D10_D11_M
VDDA 11
CLKP 12
CLKM 13
DEC 14
PWD/OE 15
OTR 16
D14_D15_M 17
D14_D15_P 18
D12_D13_M 19
D12_D13_P 20
005aaa106
36 SCLK/DFS
37 SDIO/DCS
39 SENSE
33 VDDO
40 VREF
32 D0
31 D1
terminal 1
index area
REFB
REFT
AGND
VCM
VDDA
AGND
INM
INP
AGND
1
2
3
4
5
6
7
8
9
34 DAV
35 n.c.
38 CS
terminal 1
index area
REFB
30 D2
29 D3
28 D4
27 D5
26 D6
25 D7
24 D8
23 D9
22 D10
21 D11
REFT
AGND
VCM
VDDA
AGND
INM
INP
AGND
1
2
3
4
5
6
7
8
9
ADC1610S
HVQFN40
ADC1610S
HVQFN40
VDDA 10
VDDA 10
VDDA 11
CLKP 12
CLKM 13
DEC 14
PWD/OE 15
OTR 16
D15 17
D14 18
D13 19
D12 20
005aaa105
Transparent top view
Transparent top view
Fig 2.
Pin configuration with CMOS digital outputs
selected
Fig 3.
Pin configuration with LVDS/DDR digital
outputs selected
6.2 Pin description
Table 2.
Symbol
REFB
REFT
AGND
VCM
VDDA
AGND
INM
INP
AGND
VDDA
VDDA
CLKP
CLKM
DEC
PWD/OE
OTR
ADC1610S_SER_2
Pin description (CMOS digital outputs)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
[1]
O
O
G
O
P
G
I
I
G
P
P
I
I
O
I
O
Description
bottom reference
top reference
analog ground
common-mode output voltage
analog power supply
analog ground
complementary analog input
analog input
analog ground
analog power supply
analog power supply
clock input
complementary clock input
regulator decoupling node
power down, active HIGH; output enable, active LOW
out of range
© NXP B.V. 2010. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Objective data sheet
Rev. 02 — 12 April 2010
32 D0_D1_P
39 SENSE
34 DAVM
33 VDDO
35 DAVP
40 VREF
38 CS
3 of 38
NXP Semiconductors
ADC1610S series
ADC1610S series; CMOS or LVDS DDR digital output
Pin description (CMOS digital outputs)
Pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type
[1]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
O
-
I
I/O
I
I
I/O
Description
data output bit 15 (MSB)
data output bit 14
data output bit 13
data output bit 12
data output bit 11
data output bit10
data output bit 9
data output bit 8
data output bit 7
data output bit 6
data output bit 5
data output bit 4
data output bit 3
data output bit 2
data output bit 1
data output bit 0 (LSB)
output power supply
data valid output clock
not connected
SPI clock / data format select
SPI data IO / output data standard
SPI chip select
reference programming pin
voltage reference input/output
Table 2.
Symbol
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VDDO
DAV
n.c.
SCLK/DFS
SDIO/ODS
CS
SENSE
VREF
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
4 of 38
NXP Semiconductors
ADC1610S series
ADC1610S series; CMOS or LVDS DDR digital output
Pin description (LVDS/DDR) digital outputs)
Pin
[1]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
34
35
Type
[2]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Description
differential output data D14 and D15 multiplexed, complement
differential output data D14 and D15 multiplexed, true
differential output data D12 and D13 multiplexed, complement
differential output data D12 and D13 multiplexed, true
differential output data D10 and D11multiplexed, complement
differential output data D10 and D11 multiplexed, true
differential output data D8 and D9 multiplexed, complement
differential output data D8 and D9 multiplexed, true
differential output data D6 and D7 multiplexed, complement
differential output data D6 and D7 multiplexed, true
differential output data D4 and D5 multiplexed, complement
differential output data D4 and D5 multiplexed, true
differential output data D2 and D3 multiplexed, complement
differential output data D2 and D3 multiplexed, true
differential output data D0 and D1 multiplexed, complement
differential output data D0 and D1 multiplexed, true
data valid output clock, complement
data valid output clock, true
Table 3.
Symbol
D14_D15_M
D14_D15_P
D12_D13_M
D12_D13_P
D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
DAVM
DAVP
[1]
[2]
Pins 1 to 16 and pins 36 to 40 are the same for both CMOS and LVDS DDR outputs (see
Table 2)
P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
O
Parameter
output voltage
Conditions
pins D15 to D0;
pins D15P to D0P;
pins D15M to D0M
Min
−0.4
Max
+3.9
Unit
V
V
DDA
V
DDO
T
stg
T
amb
T
j
analog supply voltage
output supply voltage
storage temperature
ambient temperature
junction temperature
−0.4
−0.4
−55
−40
-
+3.9
+3.9
+125
+85
125
V
V
°C
°C
°C
8. Thermal characteristics
Table 5.
Symbol
R
th(j-a)
R
th(j-c)
[1]
Thermal characteristics
Parameter
thermal resistance from junction to ambient
thermal resistance from junction to case
Conditions
[1]
[1]
Typ
22.5
11.7
Unit
K/W
K/W
Value for six layers board in still air with a minimum of 25 thermal vias.
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
5 of 38
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