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DAC-S
FEATURES
100MHz conversion rate
Low power, 650mW, typical
Low glitch energy, 3.0pV-s
Excellent dynamic specifications
TTL/CMOS compatible inputs
20ns settling time
Pin compatible with Analog Devices AD9713
PRODUCT OVERVIEW
The DAC-S is a 12-bit, ultra high speed, current
output digital-to-analog converter. This TTL/CMOS
compatible device converts at a rate of 100MHz
and features a 3.0pV-s glitch energy and excellent
frequency domain specifications.
The DAC-S develops complementary current
outputs of 0 to –20.48mA and can directly drive 50
Ohm loads. The excellent dynamic specifications
(to Nyquist at fOUT=2.02MHz) include an SFDR
of –85dB. Static performance includes maximum
over temperature specifications of ±.1.75LSB and
±1.5LSB for integral and differential nonlinearity,
respectively.
The DAC-S achieves low power and high speed
performance from an advanced BiCMOS process.
The architecture employs an R/2R resistor network
and a segmented switching current cell arrange-
ment to reduce glitch. Laser trimming assures that
12-bit linearity is achieved and maintained over the
transfer curve. It also incorporates a 12-bit input
data register and bandgap voltage reference with a
buffer amplifier.
The DAC-S runs on +5V and –5.2V supplies and
dissipates a maximum of 802mW. It is available in
a 28-pin CLCC package with an operating tempera-
ture range of –55 to +125°C.
FUNCTIONAL BLOCK DIAGRAM
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22 Feb 2010 MDA_DAC-S.B01
Page 1 of 7
DAC-S
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
LIMITS
+5V Digital Supply
+5.5
–5.2V Digital Supply
–5.5
–5.2V Analog Supply
–5.5
Digital Input Voltages
–0.5 to +5V Supply level
Internal Reference Output Current
±2.5
Voltage from CTRL IN to
2.5 to 0
–5.2V (A) Supply
CTRL OUT Output Current
±2.5
Reference Input Voltage Range –5.2V (A) Supply Level to –3.7
Analog Output Current, IOUT
30
Lead Temperature (10 seconds)
300
PHYSICAL/ENVIRONMENTAL
UNITS
Volts
Volts
Volts
Volts
mA
Volts
mA
Volts
mA
°C
PARAMETERS
Operating Temperature Range
Storage Temperature Range
Thermal Resistance,
θja
Junction Temperature
Package Type
—
MIN.
–55
–65
TYP.
—
—
24
—
28 Pin CLCC
+150
MAX.
+125
+150
UNITS
°C
°C
(°C/W)
°C
FUNCTIONAL SPECIFICATIONS
(TA = See specification table, –5.2V (A) Supply = –5.2V (D) Supply = –4.94 to –5.46V, +5V Supply = 4.75 to 5.25V, VREF = Internal, RL = 50 Ohms and fs = 100MHz unless otherwise
specified.)
0 TO +70°C
DIGITAL INPUTS
Resolution
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS
Data setup time, t
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLOCK Pulse Width, T
PW
1, T
PW
2
STATIC PERFORMANCE
Integral Nonlinearity
➀
Differential Nonlinearity
Offset Error
Gain Error
➁
DYNAMIC PERFORMANCE
Conversion Rate
➂
Output Voltage Settling Time, tSET
Full Scale Step to ±1LSB
Full Scale Step to ±0.5LSB
Glitch Area
Singlet (Peak)
Doublet (Net)
Output Slew Rate
Output Rise Time
Output Fall Time
Differential Gain
Differential Phase
Spurious Free Dynamic Range, S
FDR
fCLK=10MSPS, fOUT=1.23MHz
fCLK=20MSPS, fOUT=5.055MHz
fCLK=40MSPS, fOUT=16 MHz
fCLK=50MSPS, fOUT= 10.1MHz
fCLK=80MSPS, fOUT= 5.1MHz
fCLK=100MSPS, fOUT=10.1MHz
Throughput rate
ANALOG OUTPUT
Full Scale Output Current
Output Voltage Compliance
➃
MIN.
12
+2.0
—
—
—
—
3
0.5
—
3
—
—
—
—
100
—
—
—
—
900
625
425
—
—
—
—
—
—
—
—
100
—
–1.25
TYP.
—
—
—
—
—
3.0
2
0.25
4.5
—
±0.75
±0.5
0.5
3
—
11
20
2
3
1000
675
470
0.15
0.07
—
—
—
—
—
—
—
–20.48
—
MAX.
—
—
+0.8
400
700
15
—
—
7
—
±1.0
±.75
5
10
—
13
22
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+3.0
MIN.
12
+2.0
—
—
—
—
3
0.5
—
3
—
—
—
—
100
—
—
—
—
900
625
425
—
—
—
—
—
—
—
—
100
—
–1.25
–55 TO +125°C
TYP.
—
—
—
—
—
3.0
2
0.25
4.5
—
±1.0
0.5
5
3
—
12
20
2
3
1000
675
470
0.15
0.07
85
77
75
80
78
79
—
–20.48
—
MAX.
—
—
+0.8
400
700
15
—
—
7
—
±1.75
±1
5
10
—
15
22
10
—
—
—
—
—
—
82
74
71
76
75
75
—
—
+3.0
UNITS
Bits
Volts
Volts
μA
μA
pF
ns
ns
ns
ns
LSB
LSB
μA
%
MHz
ns
ns
pV-s
pV-s
V/μs
ps
ps
%
Deg
dB
dB
dB
dB
dB
dB
MSPS
mA
Volts
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Page 2 of 7
DAC-S
INTERNAL REFERENCE/AMPLIFIER
MIN.
Reference Voltage, VREF
–1.27
Reference Voltage Drift
—
Reference Current Sink/Source Capability
–125
Reference Load Regulation
(IREF = 0 to –125μA)
—
Reference Input (CTRL IN) Impedance
—
Reference Input (CTRL IN)
Multiplying Bandwidth
(100mV sine wave, to -3dB loss at IOUT)
50
Input Impedance at REF OUT
3
Amplifier Large Signal Bandwidth
(4V p-p sine wave input, to slew rate limit)
1
Amplifier Small Signal Bandwidth
(1V p-p sine wave input, to –3dB loss)
4
POWER REQUIREMENTS
Power Supply Ranges
+5V Supply
–5.2V Supplies
Power Supply Currents
+5V Supply
–5.2V Digital Supply
–5.2V Analog Supply
Power Dissipation
Power Supply Rejection (±5% variation)
0 TO +70°C
TYP.
–1.23
50
50
12
75
5
3
10
MAX.
–1.17
100
+50
—
—
—
—
—
—
MIN.
–1.27
—
–125
—
10
50
3
1
4
–55 TO +125°C
TYP.
–1.23
175
—
50
12
75
5
3
10
MAX.
–1.17
100
+50
—
—
—
—
—
—
UNITS
Volts
μV/°C
μA
μV
kOhms
MHz
kOhms
MHz
MHz
+4.75
–4.94
—
—
—
—
—5
—
—
13
70
42
650
10
+5.25
–5.46
20
85
50
800
—
+4.75
–4.94
—
—
—
—
5
—
—
13
70
42
650
10
+5.25
–5.46
20
95
50
800
μA/V
Volts
Volts
mA
mA
mA
mW
Footnotes:
➀
Best fit straight line.
➁
Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(1.28mA typ.). Ideally the ratio should be 16.
➂
Clock frequency range is from DC to the guaranteed minimum conversion rate.
➃
Dynamic Range must be limited to a 1V swing within the compliance range.
TECHNICAL NOTES
Clock Termination
The internal 12-bit register is updated on the rising edge of the Latch
Enable (pin 26). To minimize reflections and noise at high clock speeds
proper termination techniques should be used. In the PCB layout the clock
runs should be kept as short as possible and have minimal loading. The
PCB should employ a controlled characteristic line impedance (Z
0
) of 50
Ohms. A shunt termination resistor, equal to Z
0
, should be placed as close
to the CLOCK pin as possible, see Figure 2. The rise, fall and propagation
delay times will be effected by the shunt termination resistor.
Digital Inputs
The DAC-S is TTL/CMOS compatible. Data is latched by a Master register.
Outputs
The outputs I
OUT
(pin 14) and I
OUT
(pin 16) are complementary current out-
puts. Current is steered to either I
OUT
or I
OUT
in proportion to the input code.
The sum of the two currents is always equal to the full scale current minus
one LSB. See Table 1. The output can be converted to a voltage through a
load resistor, typically 50 Ohms. Both current outputs should have the same
load resistance value. See Figure 2. The output voltage generated is:
V
OUT
= I
OUT
(R
OUT
|| 227 Ohms)
where 227 Ohms is the nominal DAC output resistance.
Table 1. Input Coding Table
INPUT CODE
MSB
LSB
Iout (mA)
–20.48
–10.24
0
Iout (mA)
0
–10.24
–20.48
1111 1111 1111
1000 0000 0000
0000 0000 0000
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Page 3 of 7
DAC-S
POWER SUPPLIES
In order to reduce power supply noise separate –5.2V analog and digital
power supplies should be used. The power supply lines should be
bypassed with 0.1μF and 0.01μF ceramic capacitors placed as close to the
–5.2V analog pins (15, 25) and digital pins (12, 21) as possible. The analog
and digital power supply ground returns should be connected at one point
as close to the power source as possible. The +5V supply pin (23) should
be bypassed with a 0.1μF ceramic capacitor connected as close to the pin
as possible. See Figure 2.
REFERENCE
The internal reference is a –1.23V, typical, bandgap voltage reference. The
internal reference is connected to Reference OUT (REF OUT, pin 20) and the
internal control Amplifier (CTRL IN, pin 19). The control Amplifier OUT (CTRL
OUT, pin 18) should be connected to Reference IN (REF IN, pin17) and to
–5.2V (pin 15) Analog Supply through a 0.1μF ceramic capacitor (as shown
in figure 2) in order to improve the settling time This reduces switching
noise and improves output settling time. The Full Scale Output Current, I
OUT
(pin 14) and I
OUT
(pin 16), is controlled by the REF OUT (pin 20) voltage and
the R
SET
(pin 24) resistor through the following equation:
Full Scale I
OUT
= (REF OUT Voltage/R
SET
Resistance) x 16
The internal reference (REF OUT) may be overdriven with a more precise
external reference, capable of delivering up to 2mA, to provide better over
temperature performance.
Figure 2. Typical Connection Diagram
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Page 4 of 7
DAC-S
T
PW1
T
PW2
CLOCK
50%
t
SU
t
HLD
DATA IN
t
SU
t
HLD
t
SU
t
HLD
t
PD
t
SET
½ LSB
CHANGE
I
OUT
½ LSB
CHANGE
t
PD
t
SET
t
PD
t
SET
Figure 3a. Timing Diagram
CLOCK
50%
DATA
IN
I
OUT
t
SET
±1/2 LSB ERROR BAND
tPD
Figure 3b. Full Scale Settling Time Diagram
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