without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. A
08/14/07
1
IS25C32A
IS25C64A
PIN CONFIGURATION
8-Pin DIP, SOIC, and TSSOP
PIN CONFIGURATION
8-Pin Rotated TSSOP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
HOLD
VCC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
GND
WP
PIN DESCRIPTIONS
CS
SCK
SI
SO
GND
V
CC
WP
HOLD
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power
Write Protect
Suspends Serial Input
Chip Select (CS
The
CS
pin activates the device.
CS):
CS
Upon power-up,
CS
should follow Vcc. When the device
is to be enabled for instruction input, the signal requires
a High-to-Low transition. While
CS
is stable Low, the
master and slave will communicate via SCK, SI, and SO
signals. Upon completion of communication,
CS
must
be driven High. At this moment, the slave device may
start its internal write cycle. When
CS
is high, the
device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.
Write Protect (WP
The purpose of this input signal is
WP):
WP
to initiate Hardware Write Protection mode. This mode
prevents the Block Protection bits and the WPEN bit in
the Status Register from being altered. To cause
Hardware Write Protection,
WP
must be Low at the same
time WPEN is 1.
WP
may be hardwired to Vcc or GND.
HOLD (HOLD
This input signal is used to suspend the
HOLD):
HOLD
device in the middle of a serial sequence and temporarily
ignore further communication on the bus (SI, SO, SCK).
Together with Chip Select, the
HOLD
signal allows
multiple slaves to share the bus. The
HOLD
signal
transitions must occur only when SCK is Low, and be
held stable during SCK transitions. (See Figure 8 for
Hold timing) To disable this feature,
HOLD
may be
hardwired to Vcc.
PIN DESCRIPTIONS
Serial Clock (SCK):
This timing signal provides synchro-
nization between the microcontroller and IS25C32A/64A.
Op-Codes, byte addresses, and data are latched on SI
with a rising edge of the SCK. Data on SO is refreshed
on the falling edge of SCK for SPI modes (0,0) and (1,1).
Serial Data Input (SI):
This is the input pin for all data
that the IS25C32A/64A is required to receive.
Serial Data Output (SO):
This is the output pin for all
data transmitted from the IS25C32A/64A.
2
Integrated Silicon Solution, Inc.
Rev. A
08/14/07
IS25C32A
IS25C64A
SERIAL INTERFACE DESCRIPTION
MASTER:
The device that provides a clock signal.
SLAVE:
The IS25C32A/64A is a slave because the
clock signal is an input.
TRANSMITTER/RECEIVER:
The IS25C32A/64A has
both data input (SI) and data output (SO).
MSB:
The most significant bit. It is always the first bit
transmitted or received.
OP-CODE:
The first byte transmitted to the slave
following
CS
transition to LOW. If the OP-CODE is a
valid member of the IS25C32A/64A instruction set (Table
3), then it is decoded appropriately. If the OP-CODE is
not valid, and the SO pin remains in high impedance.
BLOCK DIAGRAM
VCC
GND
STATUS
REGISTER
8192 x 8/4096 x 8
MEMORY ARRAY
DATA
REGISTER
SI
MODE
DECODE
LOGIC
ADDRESS
DECODER
OUTPUT
BUFFER
CS
WP
SCK
CLOCK
SO
HOLD
Integrated Silicon Solution, Inc.
Rev. A
08/14/07
3
IS25C32A
IS25C64A
STATUS REGISTER
The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is
accessible by the user.
Block Protect (BP1, BP0), Bits 2-3:
Together, these
bits represent one of four block protection configurations
implemented for the memory array. (See Table 2 for
details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block of
memory defined by these bits is always protected,
regardless of the setting of WPEN,
WP
, or WEN.
Table 1. Status Register Format
Bit 7
WPEN
Bit 6 Bit 5 Bit 4
X
X
X
Bit 3 Bit 2
Bit1 Bit 0
BP1 BP0 WEN
RDY
Notes:
1. X = Don't care bit.
2. During internal write cycles, bits 0 to 7 are temporarily 1's.
Table 2. Block Protection
Status
Register
Bits
Level
0
1(1/4)
2(1/2)
3(All)
BP1
0
0
1
1
BP0
0
1
0
1
The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 0. If
neither is true, it can be modified by a valid instruction.
Ready (RDY Bit 0:
When
RDY
= 1, it indicates that
RDY),
RDY
the device is busy with a write cycle.
RDY
= 0 indi-
cates that the device is ready for an instruction. If
RDY
= 1, the only command that will be handled by the
device is Read Status Register.
Write Enable (WEN), Bit 1:
This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modifica-
tion, regardless of the setting of WPEN,
WP
pin, or block
protection. The only way to set WEN to 1 is via the
Write Enable command (WREN). WEN is reset to 0
upon power-up.
Array Addresses Protected
IS25C32A
None
0C00h
-0FFFh
0800h
-0FFFh
0000h
-0FFFh
IS25C64A
None
1800h
-1FFFh
1000h
-1FFFh
0000h
-1FFFh
Don’t Care, Bits 4-6:
Each of these bits can receive
either 0 or 1, but values will not be retained. When
these bits are read from the register, they are always 0.
Write Protect Enable (WPEN), Bit 7:
This bit can be
used in conjunction with
WP
pin to enable Hardware
Write Protection, which causes the Status Register to
be read-only. The memory array is not protected by this
mode. Hardware Write Protection requires that
WP
= 0
and
WPEN = 1; it is disabled otherwise. Note: WPEN
cannot be changed from 1 to 0 if the
WP
pin is already
set to Low. (See Table 4 for data protection relationship)
4
Integrated Silicon Solution, Inc.
Rev. A
08/14/07
IS25C32A
IS25C64A
DEVICE OPERATION
T
he operations of the IS25C32A/64A are controlled by a set of instructions that are clocked-in serially SI pin. (See
Table 3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High
transition of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to
continue to input an address or data to SI, or to output data from SO. During data output, values appear on the falling
edge of SK. All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-
to-High transition of SK,
CS
should be raised High to end the transaction. The device then would enter Standby Mode
if no internal programming were underway.
Table 3. Instruction Set
Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Op-code
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Array
Write Data to Array
Address
-
-
-
-
A15-A0
A15-A0
Data(SI)
-
-
-
D7-D0
-
D7-D0,...
Data (SO)
-
-
D7-D0,...
-
D7-D0,...
-
1. X = Don’t care bit. For consistency, it is best to use “0”.
2. Some address bits are don’t care. See Table 5.
3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon
CS
going High there is no
affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the
array or Status Register to be ignored.
WRITE ENABLE (WREN)
When Vcc is initially applied, the device powers up with
both status register and entire array in a write-disabled
state. Upon completion of Write Disable (WRDI), Write
Status Register (WRSR), or Write Data to Array
(WRITE), the device resets the WEN bit in the Status
Register to 0. Prior to any data modification, a WREN
instruction is necessary to set WEN to 1. (See Figure 2
for timing).
WRITE DISABLE (WRDI)
The device can be completely protected from modifica-
tion by resetting WEN to 0 through the WRDI instruc-
tion. (See Figure 3 for timing).
READ STATUS REGISTER (RDSR)
The Read Status instruction tells the user the status of
Write Protect Enable, the Block Protection setting (see
Table 2), the Write Enable state, and the
RDY
status.
RDSR is the only instruction accepted when a write
cycle is underway. It is recommended that the status of
Write Enable and
RDY
be checked, especially prior to
an attempted modification of data. The 8 bits of the
Status Register can be repeatedly output on SO after
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